Write-acknowledge circuit including a write detector and a bista

Details Write-acknowledge circuit including a write detector and a bista Write-acknowledge circuit including a write detector and a bista

1991-02-21

1994-01-18

Gosssage, Glenn

Static information storage and retrieval

Magnetic bubbles

Guide structure

395550, 395325, 365233, 3072721, 307279, 307571, 307584, 3072471, G06F 1342, H03K 17687, H03K 3356

Patent

active

052805964

ABSTRACT:
A write-acknowledge circuit includes a write detector and a bistable element. The write detector has two write inputs, two complementary inputs and an acknowledge output, and is constituted by only two transistors which are connected in series. The complementary inputs are the control inputs of the two transistors and the acknowledge output is output from their common connection point. The write inputs are respectively coupled to the two remaining terminals of the two transistors and also to the two respective inputs of the bistable element. The complementary inputs are coupled crosswise to the outputs of the bistable element. The write signals represent a 1-bit variable encoded according to the Double-Rail Encoding method. Four-phase handshake signalling is used for the write signals. The acknowledge output is activated by the complementary inputs to the write detector in response to a write signal on either of the two write inputs, the acknowledge signal denoting that the write signal has been processed by the write-acknowledge circuit and so can be permitted to return to a rest value.

REFERENCES:
patent: 3812388 (1974-05-01), Southworth
patent: 4390969 (1983-06-01), Hayes
patent: 4534011 (1985-08-01), Andrews et al.
patent: 4563599 (1986-01-01), Donoghue et al.
patent: 4598216 (1986-07-01), Lauffer et al.
patent: 4692635 (1987-09-01), Rapp
patent: 4751683 (1988-06-01), Wada et al.
patent: 4791614 (1988-12-01), Arakawa
patent: 4937792 (1990-06-01), Suzuki et al.
patent: 4982117 (1991-01-01), Matsuzaki et al.
patent: 5005136 (1991-04-01), Van Berkel et al.
patent: 5070443 (1991-12-01), Priem et al.
Sood et al., "A Fast 8K.times.8 CMOS SRAM With Internal Power Down Design Techniques," IEEE Journal of Solid State Circuits, vol. SC-20, No. 5, Oct. 1985, pp. 941-945.
"Static RAM Input Buffer and Its Transition Detector," IBM Tech. Disc. Bull., vol. 27, No. 10B, Mar. 1985, pp. 6189-6191.

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