Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – Addressing cache memories
Patent
1995-12-27
1998-12-01
Moore, David K.
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
Addressing cache memories
711113, 711118, 711119, 711136, G06F 926, G06F 1202
Patent
active
058453083
ABSTRACT:
A "wrapped-line" direct-mapped cache is disclosed that stores words with main-memory addresses that succeed a requested address where a conventional nonwrapped direct-mapped line-unit cache would store words with main-memory addresses that precede the requested memory address. Since succeeding addresses are more likely to be called "soon" after a requested address, the wrapped-line direct-mapped cache provides more efficient use of cache capacity, and thus more effectively enhances the performance of an incorporating system. The wrapped-line direct-mapped cache has indexed storage locations. Each storage location has sections for storing a tag, a string-boundary indicator, and a line of words. Each storage location has a line index, and each word position in a line has a word-position index. To determine whether a requested address results in a hit or a miss, the match logic divides the requested address into high, intermediate, and low segments. The hit-or-miss determination is made by examining the tag and string-boundary sections of the "requested" cache storage location (indexed by intermediate bits of the requested address) as well as of the predecessor storage location. In the event of a hit, the requested word is transmitted from the cache for processing by a microprocessor. In the event of a miss, the high segment is stored in the tag section of the requested storage location to serve as a tag. In addition, the low segment of the requested address is stored in the string-boundary section of the requested storage location to serve as a string-boundary indicator. The requested and successor addresses are transmitted to main memory so that each word so fetched is stored at a word position having its word-position index equaling the word's main-memory-address low segment. The requested word is forwarded from the cache for processing by the microprocessor.
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Anderson Clifton L.
Moore David K.
Nguyen Than V.
VLSI Technology Inc.
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