Wrap-around mechanism for memory split-wordline read

Details Wrap-around mechanism for memory split-wordline read Wrap-around mechanism for memory split-wordline read

1996-08-13

1998-09-08

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711154, 36523003, 36523006, G06F 1206, G11C 11407

Patent

active

058060820

ABSTRACT:
A memory with at least two banks, each bank capable of storing N=2.sup.n unique lines of data, each line of data addressable by an n-bit code corresponding to an address index i, 0.ltoreq.i.ltoreq.N-1, provides for operation in either an OR-line or split-line mode. In the OR-line mode, data from line i, corresponding to index i, is available from all banks. In the split-line mode, data is available from line address i of one set of banks, and address i+1 from another set of banks. In either mode, wrap-around from line address i=N-1 to i=0 is provided by the use of an additional line of memory located at a position corresponding to i=N that contains the same data as the line corresponding to i=0. In this manner, a complete wrap-around read capability is provided without suffering a memory speed loss.

REFERENCES:
patent: 5257235 (1993-10-01), Miyamoto

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