Wrap-around gate field effect transistor

Details Wrap-around gate field effect transistor Wrap-around gate field effect transistor

2007-09-18

2007-09-18

Menz, Douglas M. (Department: 2891)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S401000

Reexamination Certificate

active

10732958

ABSTRACT:
A field effect transistor is formed having wrap-around, vertically-aligned, dual gate electrodes. Starting with an silicon-on-insulator (SOI) structure having a buried silicon island, a vertical reference edge is defined, by creating a cavity within the SOI structure, and used during two etch-back steps that can be reliably performed. The first etch-back removes a portion of an oxide layer for a first distance over which a gate conductor material is then applied. The second etch-back removes a portion of the gate conductor material for a second distance. The difference between the first and second distances defines the gate length of the eventual device. After stripping away the oxide layers, a vertical gate electrode is revealed that surrounds the buried silicon island on all four side surfaces.

REFERENCES:
patent: 5801397 (1998-09-01), Cunningham
patent: 6413802 (2002-07-01), Hu et al.
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6563131 (2003-05-01), Adkisson et al.
patent: 6833588 (2004-12-01), Yu et al.
patent: 7074656 (2006-07-01), Yeo et al.

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