Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-13
2001-09-04
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185220
Reexamination Certificate
active
06285594
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to non-volatile memory devices and, more particularly, to methods and systems of preventing undesirable voltage on a plurality of wordlines in flash electrically erasable programmable read-only memory (EEPROM).
BACKGROUND OF THE INVENTION
A flash memory is a storage device that is capable of retaining stored information in the absence of continuous power. The information is stored in a plurality of flash transistors that are electrically connected and formed on a silicon substrate. A flash transistor is typically referred to as a cell and includes a source, a drain, a floating gate and a control gate. Flash memory devices are formed with rows and columns of flash transistors that form a flash transistor array of cells that are referred to as core memory cells. The flash transistor array is in the form of a matrix where typically the control gates of the core memory cells are electrically connected with a respective wordline such that a wordline decoder can direct a plurality of operational voltages to the wordlines. The drains of the core memory cells are typically electrically interconnected to form bitlines such that a bit line decoder directs a plurality of operational voltages to the bitlines. Generally, the sources of the core memory cells are electrically interconnected to form a common sourceline and are controlled by a sourceline controller.
To program a respective core memory cell in the flash memory, the control gate (wordline) and drain (bitline) of the cell to be programmed are raised to predetermined programming voltages and the source is grounded. When the predetermined programming voltages are removed, a negative charge on the floating gate is maintained. In contrast to the programming procedure, flash memory devices are typically bulk erased, so that all of the core memory cells on a predetermined number of bitlines and wordlines are simultaneously erased by applying predetermined voltages to the bitlines, the wordlines and the source line. Prior to the bulk erase, the core memory cells are pre-programmed since all cells must be programmed prior to erase to avoid over erasure as known in the art.
In order to read a given cell, a voltage called the threshold voltage of the cell is measured to determine if the cell is in a charged (programmed) or an uncharged (un-programmed) state. Core memory cells are read by applying a predetermined voltage to the wordline and the bitline, grounding the source line and then sensing the current on the bitline. If the core memory cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero, or at least relatively low, when the predetermined voltage is applied between the control gate and the drain of the core memory cell. If the core memory cell is not programmed, the threshold voltage will be relatively low and the bitline current will be relatively high when the predetermined voltage is applied.
Typically, programming and erasing cells includes verification to confirm the threshold voltage is at the correct magnitude for the desired state of the cells. Verification is accomplished by methods known in the art as a program verify and an erase verify. The program verify and erase verify involve reading the state of cells previously subjected to the predetermined program and erase voltages and taking corrective actions that include further programming and erasing if the magnitude of the threshold voltage is incorrect.
The threshold voltage is typically determined from the bitline current of the core memory cells during the program verify and erase verify by reading and comparing the bitline current of the core memory cells with a reference current in a sensing circuit. In general, if the core memory cell conducts a current greater than or equal to the reference current, it is un-programmed and if the core memory cell conducts a current less than the reference current, it is programmed. The reference current is generated from a group of reference memory cells in the sensing circuit that are subjected to the same wordline and bitline voltages as the core memory cells targeted for programming or erasing.
In prior art flash memory utilizing 0.25 micron process technology, the wordlines of the core memory cells and the reference memory cells are typically supplied voltage during embedded modes when the flash memory is not in auto power-down mode. As known in the art, the auto power-down mode is a “sleep” mode that removes the supply voltage (Vcc) from the flash memory during periods of inactivity to conserve power. When not in the auto power-down mode, prior art flash memory with direct current (dc) sensing typically has voltage supplied to the wordlines during embedded modes even when a function that includes the programming, erasing or reading of the cells is not occurring. Prior art flash memory with alternate current (ac) sensing may also have voltage supplied to the wordlines during embedded modes for an indefinite period.
A known problem can arise when the magnitude and/or duration of voltage supplied to the wordlines when no function is occurring is such that the cells electrically connected with the wordlines are disturbed. As known in the art, when the cells electrically connected with the wordlines are disturbed, single bit charge gain can occur. Single bit charge gain causes the threshold voltage of the cells to change thereby causing errors and reliability problems when the cells are read. In addition, another known problem involves the power consumed by the wordline decoder when voltage is supplied to the wordlines while no function is occurring.
To that end, a need exists for methods and systems capable of allowing voltage to be applied to the wordlines only when the cells on the wordlines are being read, programmed or erased.
SUMMARY OF THE INVENTION
The present invention discloses systems and methods of providing a predetermined voltage to at least one wordline in a memory device that in the preferred embodiment is a flash memory. In the preferred flash memory, voltage is supplied to the wordlines only when core memory cells on the selected wordlines are being read, programmed or erased. As such, the core memory cells will not be disturbed and power consumption by the flash memory is minimized during operation. As known in the art, disturbance of the core memory cells can cause errors and reliability problems when the core memory cells are read during use to retrieve data stored in the flash memory.
The preferred flash memory includes at least one wordline voltage supply circuit, at least one decoder circuit, a wordline voltage protection circuit and at least one wordline. In the preferred embodiment of the invention, the wordline voltage supply circuits are electrically connected with the decoder circuits and the wordline voltage protection circuit. The decoder circuits are also electrically connected with the wordline voltage protection circuit and the wordlines.
During operation of the preferred flash memory, the wordline voltage supply circuits generate a predetermined voltage for the wordlines depending upon which designated function is being performed. The voltages that may be supplied by the wordline voltage supply circuits during operation include a supply voltage (Vcc), a predetermined erase verify voltage, a predetermined program verify voltage and a predetermined program voltage. The voltage generated by the wordline voltage supply circuits is supplied to the decoder circuits. The decoder circuits comprise a plurality of wordline decoders that are only enabled when the wordline voltage protection circuits activate the decoder circuits. Once the decoder circuits are activated, the wordlines are decoded and the voltage supplied by the wordline voltage supply circuits is transferred to the wordlines by the selected decoders.
The wordline voltage protection circuit activates the decoder circuits during a read or a write mode in the flash memory. Those skilled in the art would recognize that the core memory ce
Bautista, Jr. Edward V.
Bill Colin S.
Yachareni Santosh K.
Advanced Micro Devices , Inc.
Ho Hoai V.
Wagner , Murabito & Hao LLP
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