Wordline resistance reduction method and structure in an...

Details Wordline resistance reduction method and structure in an... Wordline resistance reduction method and structure in an...

2011-01-11

2011-01-11

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S656000, C257SE21296, C257SE21622, C257SE21636, C257S388000

Reexamination Certificate

active

07867899

ABSTRACT:
Methods and structures for reducing resistance in wordlines of an integrated circuit memory device are disclosed. In one embodiment, the method includes forming multiple columns of polycrystalline silicon for respective number of wordlines, forming core transistor junctions and periphery transistor junctions associated with the wordlines, performing a salicidation process for the periphery transistor junction and performing a salicidation process for the columns of polycrystalline silicon to from the wordlines with low resistance.

REFERENCES:
patent: 6809018 (2004-10-01), Chung
patent: 2005/0191833 (2005-09-01), Chang et al.
patent: 2006/0261418 (2006-11-01), Eitan et al.

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