Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-12-04
2003-12-02
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S201000
Reexamination Certificate
active
06657915
ABSTRACT:
The present application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 2000-73802 filed on Dec. 6, 2000, which is hereby incorporated by reference in its entirety for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a wordline driver for ensuring equal stress to wordlines in a multi row address disturb test and a method of driving the wordline driver.
2. Description of the Related Art
As the storage capacity of semiconductor memory devices increases, the time required to test semiconductor memory devices increases. To reduce the test time, particularly for a dynamic random access memory, a method of enabling a plurality of wordlines simultaneously is sometimes used instead of a method of enabling one wordline for the test. The process in which one wordline is enabled to sense a memory cell data is called a “disturb”, and the process in which a plurality of wordlines are enabled to sense the data of a plurality of memory cells simultaneously, is called a multi-row address disturb (MRAD). Therefore, the MRAD mode is advantageous in reducing the time required to test a semiconductor memory device in comparison to the disturb mode.
The structure of a circuit enabling wordlines and the operation timing diagram thereof are illustrated in
FIGS. 1 through 4
.
FIG. 1
is a diagram illustrating a conventional row address pre-decoder
100
. The row address pre-decoder
100
combines externally input row addresses RA
0
through RA
11
and then generates address decoding signals DRA
01
through DRA
91011
. The address decoding signal DRA
01
is a signal made by combining the row addresses RA
0
and RA
1
. The address decoding signal DRA
234
is a signal made by combining the row addresses RA
2
, RA
3
, and RA
4
. The address decoding signals DRA
56
, is made by combining the row address signals RA
5
and RA
6
, and the address decoding signals DRA
78
is made by combining the row address signals RA
7
and RA
8
. Finally, the address decoding signal DRA
91011
is made by combining the row address signals RA
9
, RA
10
and RA
11
.
FIG. 2
is a diagram illustrating a sub-wordline decoder
200
. The sub-wordline decoder
200
generates sub-wordline signals PXi and PXiB through the combination of the address decoding signals DRA
01
and DRA
91011
. As the sub-wordline decoder is driven by a boosting voltage Vpp, the voltage level of the sub wordline signals PXi and PXiB appears to be the boosting voltage Vpp.
FIG. 3
is a diagram illustrating a conventional wordline driver
300
. The wordline driver
300
includes a main decoder
310
and a driver
320
. The main decoder includes a PMOS transistor
311
that responds to a pre-charge signal PRECH; NMOS transistors
312
,
313
,
314
and
315
connected in series, that respond to the address decoding signals DRA
234
, DRA
56
, DRA
78
and DRA
91011
, respectively; and an inverter
316
that responds to a node A placed between the PMOS transistor
311
and the first NMOS transistor
312
. The output of the inverter
316
becomes a normal wordline enable signal NWEi. A driver
320
includes an NMOS transistor
321
which transmits the normal wordline enable signal NWEi to a node B in response to the boosting voltage Vpp, an NMOS transistor
322
which transmits the normal wordline enable signal NWEi to a wordline WLi in response to the sub-wordline signal PXi, an NMOS transistor
323
which transmits the sub-wordline signal PXi to the wordline WLi in response to the voltage of the node B, and an NMOS transistor
324
which discharges the wordline WLi to ground in response to the complementary sub-wordline signal PXiB.
The operation of the MRAD mode illustrated in
FIGS. 1 through 3
will be described with reference to the timing diagram of FIG.
4
. Referring to
FIG. 4
, a sub-wordline signal PXi and normal wordline enable signals NWE
0
, NWE
1
, NWE
2
and so on are generated by receiving address signals ADDR in every row active command interval. The first normal wordline enable signal NWE
0
generated in a first row active command interval P
1
and the sub-wordline signal PXi generate a wordline WL
0
and also selectively generate WL
1
through WL
3
(not shown). The second normal wordline enable signal NWE
1
generated in a second row active command interval P
2
and the sub-wordline signal PXi generate a wordline WL
4
and selectively generate WL
5
through WL
7
(not shown). The third normal wordline enable signal NWE
2
generated in a third row active command interval and the sub-wordline signal PXi generate a wordline WL
8
and selectively generate wordlines WL
9
through WL
11
(not shown).
In the first row active command interval P
1
, the first normal wordline enable signal NWE
0
of the boosting voltage Vpp is transmitted to the node B of
FIG. 3
, and subsequently the sub-wordline signal PXi is coupled to the node B by a gate-source capacitance of the NMOS transistor
323
, known as a self-boosting phenomenon. Consequently, the node B has a voltage of 2 Vpp−Vt and the first wordline WL
0
is at the boosting voltage Vpp.
On the contrary, in the second row active command interval P
2
, the second normal wordline enable signal NWE
1
is at the boosting voltage Vpp and the sub-wordline signal PXi is in an already enabled condition so as to be at the boosting voltage Vpp. Consequently, the node B is at the voltage level of Vpp−Vt. Then, the fifth wordline WL
4
is at the voltage level of Vpp−2 Vt. In the same way, the ninth wordline WL
8
is at the voltage level of Vpp−2 Vt in the third row active command interval P
3
.
In other words, during the test in the MRAD mode, the voltage level of the first wordline WL
0
is different from that of the subsequent wordlines including the fifth and ninth wordlines WL
4
and WL
8
and so on, because of the fact that the former is Vpp and the latter are Vpp−2 Vt. If an NMOS transistor is used as a cell transistor, a high voltage must be applied to the cell gate for the purpose of preventing loss of memory cell data. At this time, if the fifth and ninth wordlines WL
4
and WL
8
are set to be at the Vpp voltage, the first wordline WL
0
is at the voltage level of Vpp+2 Vt. Consequently, the first wordline WL
0
is over-stressed by 2 Vt compared to the fifth and ninth wordlines WL
4
and WL
8
. Memory cells which are connected to the first wordline WL
0
and which are consequently over-stressed, can cause reliability problems with respect to a gate oxide layer.
Therefore, a wordline driver which can prevent a firstly-enabled wordline in which a self-boosting phenomenon occurs from being over-stressed during a test in the MRAD mode, and a corresponding driving method, are needed to overcome such problems.
SUMMARY OF THE INVENTION
The present invention is therefore directed to a wordline driver, and method of driving the wordline driver, which substantially overcome one or more of the problems due to the limitations and disadvantages of the related art.
To solve the above problems, it is an object of the present invention to provide a wordline driver which can apply equal stress to each wordline during a multi-row address disturb test in which a plurality of wordlines are sequentially enabled, so that an equal stress is applied to each of the wordlines.
It is another object of the present invention to provide a corresponding method of driving the wordline driver.
Accordingly, to achieve the first and other objects of the invention, there is provided a wordline driver including a control unit which generates decoder control signals from predetermined signals among externally input address decoding signals in response to signals of a multi-row address disturb (MRAD) mode in which a plurality of wordlines are sequentially enabled, a decoder which generates normal wordline enable signals in response to the address decoding signals and the decoder control signals, and a driver which drives sub-wordline signals generated by combining the address
Seo Young-soon
Son Tae-sik
Auduong Gene N
Samsung Electronics Co,. Ltd.
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