Static information storage and retrieval – Read/write circuit – Including magnetic element
Reexamination Certificate
2002-04-10
2004-10-26
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Including magnetic element
C365S158000
Reexamination Certificate
active
06809981
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the reading of resistor-based memory devices such as magnetic resistive random access memory (MRAM) devices which store logic values as resistive states in a memory cell.
2. Description of the Related Art
FIG. 1
shows one example of a resistor based memory array architecture called a crosspoint array architecture. The memory array
8
includes a plurality of row lines
10
arranged in orgthogonal orientation to a plurality of column lines
12
. Each row line is coupled to each of the column lines by a respective resistive memory cell
14
. Each memory cell stores one of two or more logical values depending on which of a plurality of resistance values it is programmed to exhibit.
An MRAM device is one approach to implementing a resistance based memory. In an MRAM, each resistive memory cell typically includes a pinned magnetic layer, a sense magnetic layer and a tunnel barrier layer between the pinned and sense layers. The pinned layer has a fixed magnetic alignment and the magnetic alignment of the sense layer can be programmed to different orientations. The resistance of the cell varies, depending on the magnetic alignment of the sense layer. One resistance value, e.g., a higher value, may be used to signify a logic “one” while another resistance value, e.g., a lower value, may be used to signify a logic “zero”. Stored data can be read by sensing the resistance of the cells, and interpreting the resistance values thus sensed as logic states of the stored data.
For MRAM sensing purposes, the absolute magnitude of memory cell resistance need not be known; only whether the resistance is above or below a threshold value that is intermediate to the logic one and logic zero resistance values. Nonetheless sensing the logic state of an MRAM memory element is difficult because the technology of the MRAM device imposes multiple constraints. In particular, the need for high storage density and low cost motivates minimizing the number of transistors in the memory array. A cell of a crosspoint array, as discussed above, does not include a transistor. As a result, each resistive element remains operatively connected to respective row and column lines at all times. Consequently, as a memory cell is sensed it is shunted by a significant leakage current path. In a conventional MRAM device, an element in a high resistance state may have a resistance of about 1 M&OHgr;, while an element in a low resistance state may have a resistance of about 950 K&OHgr;. The differential resistance between a logic one and a logic zero is thus about 50 K&OHgr;, or 5% of scale. Rapidly distinguishing a 5% resistance differential on a scale of 1 M&OHgr; in the face of low resistance leakage paths and with a minimum of circuitry is a challenge. While various schemes have been proposed for sensing the resistance of resistive memory cells, room for improvement remains.
In one previously considered approach to MRAM cell sensing, the rows and columns of an array of MRAM memory cells are quiescent at a potential known as array voltage that is different from ground potential. During a data read, one of the row lines is grounded and a resulting current flow, through a column line and through a connected target memory cell, is measured. An MRAM memory array according to this approach is illustrated in FIG.
2
.
FIG. 2
shows a plurality of row lines
10
connected to a respective plurality of voltage sources
24
. Each row line is operatively connected to a plurality of memory cells
14
. The memory cells are connected to a respective plurality of column lines
12
, and the column lines are connected to respective sensing circuits
22
to detect current flowing into the respective column lines. When one row line
28
of the plurality of row lines
10
is switchingly grounded, as shown at
26
, current flows through the memory cells connected to that grounded row line
28
.
FIG. 3
shows one particular memory cell
38
connected to the grounded row line
28
. The current flowing through memory cell
38
is sourced by a particular column line
30
, and detected by a particular sensing circuit
32
connected to the particular column line
30
. By sensing the magnitude of the current in the particular column line
30
, the particular sensing circuit
32
determines the resistance, and thus the programmed logic state, of memory cell
38
.
When the switch
26
grounds row line
28
current flows through memory cell
38
and column line
30
. Sensing circuit
32
detects this current and ascertains the logic state of memory cell
38
. Other memory elements, e.g.,
34
,
40
,
42
,
44
, and
46
are also connected to the column line
30
. Leakage current through these other memory elements is minimized by maintaining the respective row lines
10
, to which these other memory elements are connected, at array voltage (Va)
24
which is substantially the same as the voltage of column line
30
. Nevertheless, some current flows through the other memory elements because of imperfect control of the array voltage delivered by column line
30
. Also, because the entire array, except for a momentarily grounded row line, is maintained at array voltage (Va), leakage current from the array causes some dissipation of energy on an ongoing basis.
BRIEF SUMMARY OF THE INVENTION
The present invention provides an MRAM sensing system which maintains a quiescent memory array at ground potential. According to the present invention the column lines of the array are allowed to float; that is they are not directly connected to a source of constant potential such as ground or array voltage (Va). The row lines are switchingly connected alternately between a source of ground potential and a source of array voltage Va. The default connection is to ground. Consequently, under default conditions any charge disposed on the floating column lines is dissipated through the memory cells, and thereafter through the row lines, to ground. In the resulting quiescent state, the entire array (row lines, memory elements, and column lines), is at ground potential and draws no current.
When the stored logical state of a particular memory cell is to be sensed, the row line to which that particular memory cell is directly connected is switched to a source of array voltage (Va). In the resulting circuit configuration, the memory cell to be sensed forms a voltage divider with respect to the other memory cells connected to the same column line. Current flows through the memory cell to be sensed to the sensed column line to which it is connected, and from that column line through the other memory cells connected to that column line to a ground potential node.
As this current flows through the voltage divider thus formed, a sensing voltage develops on the sensed column line related to the logical state of the particular memory cell being sensed. An amplifier connected to the sensed column line detects and amplifies this voltage to discriminate the logic state of the particular memory cell.
These and other aspects and features of the invention will be more clearly understood from the following detailed description which is provided in conjunction with the accompanying drawings.
REFERENCES:
patent: 6259644 (2001-07-01), Tran et al.
patent: 6462979 (2002-10-01), Schlosser et al.
patent: 6490190 (2002-12-01), Ramcke et al.
patent: 2002/0126524 (2002-09-01), Sugibayashi et al.
patent: 2002/0135018 (2002-09-01), Hidaka
patent: 2002/0136047 (2002-09-01), Scheuerlein
patent: 2003/0002333 (2003-01-01), Hidaka
Dickstein , Shapiro, Morin & Oshinsky, LLP
Elms Richard
Hur J. H.
Micro)n Technology, Inc.
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