Wordline decoder of non-volatile memory device using HPMOS

Details Wordline decoder of non-volatile memory device using HPMOS Wordline decoder of non-volatile memory device using HPMOS

2007-10-30

2007-10-30

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230080, C365S189050

Reexamination Certificate

active

11383064

ABSTRACT:
A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

REFERENCES:
patent: 5949735 (1999-09-01), Jeong
patent: 6411554 (2002-06-01), Kawai
patent: 6587375 (2003-07-01), Chung et al.

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