Word line to bit line spacing method and apparatus

Details Word line to bit line spacing method and apparatus Word line to bit line spacing method and apparatus

2008-06-06

2010-11-23

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S296000, C257S326000

Reexamination Certificate

active

07838928

ABSTRACT:
In one embodiment, a memory cell includes a bit line arranged in a semiconductor substrate and a bit line contact region arranged adjacent the bit line. A word line is arranged above the bit line contact region in a trench formed in the semiconductor substrate. A generally U-shaped insulating layer is arranged in a bottom region of the trench and separates the bit line and the bit line contact region from the word line.

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“DRAM Makers Cut Cost by 30% a Year to 2011”, Nikkei Electronics Asia—Jan. 2008, http://techon.nikkeibp.co.jp/article/HONSHI/20071219/144399.

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