Word line loading compensating circuit of semiconductor memory d

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

36518911, 365194, 365204, G11C 800

Patent

active

055047157

ABSTRACT:
A word line loading compensating circuit compensates a word line boosted voltage level changed in accordance with a word line loading. A word line boosting circuit outputs a word line boosted voltage boosted over a power supply voltage input from the exterior of a chip, so as to boost a voltage of the word line connected to the memory cell array. A row decoder is connected to the word line boosted voltage output from the word line boosting circuit and selects a memory cell from an array of memory cells in correspondence with a predetermined row address signal. A capacitor connected between the word line boosted voltage and the row decoder stores a charge from the word line boosted voltage. A variable connecting device connects the word line boosted voltage to the capacitor before the word line boosted voltage reaches a saturation level, and cuts off the word line boosted voltage from the capacitor after the word line boosted voltage reaches the saturation level. A delay device inputs the word line boosted voltage, delays the input word line boosted voltage during the arrival time of the saturation level, and generates a delay output signal which controls the variable connecting device. A discharging device is controlled by the delay output signal and discharges the charge stored in the capacitor to ground after the word line boosted voltage reaches the saturation level.

REFERENCES:
patent: 4896297 (1990-01-01), Miyatake et al.
patent: 4967399 (1990-10-01), Kuwabara et al.
patent: 5010259 (1991-04-01), Inoue et al.
patent: 5185721 (1993-02-01), Love et al.
patent: 5404330 (1995-04-01), Lee et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Word line loading compensating circuit of semiconductor memory d does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Word line loading compensating circuit of semiconductor memory d, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Word line loading compensating circuit of semiconductor memory d will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-2021742

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.