Word-line driving circuit and semiconductor memory device

Details Word-line driving circuit and semiconductor memory device Word-line driving circuit and semiconductor memory device

2000-03-01

2001-03-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230030, C365S230080

Reexamination Certificate

active

06198685

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a word-line driving circuit and a semiconductor memory device, and more particularly to the word-line driving circuit for the semiconductor memory device which needs a high voltage for read/write operations.
2. Description of the Related Art
In a semiconductor memory device, for a plurality of memory elements arranged in a bit-line direction for each block, a word-line driving circuit is provided for each of word lines in the block, so that the circuit may be selected in response to addressing, to drive the corresponding word line for performing write-in, read-out, and erasure operations to a corresponding memory cell.
FIG. 16
exemplifies a conventional word-line driving circuit, which is shown to comprise: P-channel type transistors
101
and
102
which constitute a flip-flop configuration switching circuit; N-channel transistors
103
and
104
which each act as a switch; a NOR circuit
105
which performs logical operations on a signal obtained by decoding high-order addresses and a signal obtained by decoding low-order addresses; and an inverter
106
which inverts an output signal of the NOR circuit
105
.
In the conventional word-line driving circuit shown in
FIG. 16
, when both a high-order select signal BXMi for specifying high-order addresses in a memory-cell array and a low-order select signal BXSi are of a high level, the NOR circuit
105
provides a high-level output, which turns on the N-channel type transistor
103
and off the N-channel type transistor
104
, which in turn turns on the P-channel type transistor
102
, thus supplying a word line Wi with a power-supply voltage Vcc or a step-up voltage Vpp. When, on the other hand, either one or both of the high-order select signal BXMi and the low-order select signal BXSi are of a high level, the NOR circuit
105
provides a low-level output, which turns off the N-channel type transistor
103
and on the N-channel type transistor
104
, thus disconnecting the word line Wi from the VCC/Vpp to reset it to a ground level (GND).
A circuit configuration similar to the above-mentioned word-line driving circuit is disclosed in for example Japanese Laid-Open Patent Application No. Hei9-17189.
The word-line driving circuit shown in
FIG. 16
, however, each requires a total of 10 transistors: two P-channel type transistors, two N-channel type transistors, four transistors in the NOR circuit, and two transistors in the inverter.
The above-mentioned semiconductor memory device requires one word-line driving circuit for each word line, a total of which circuit numbers a tremendous value with a recent-year semiconductor mass-storage device of an ever increasing integration density, so that when the above-mentioned word-line driving circuit requiring many transistors is employed, the circuitry size increases too much, thus adding to a chip size of a semiconductor IC to which a memory device is contained.
With an increasing degree of fine patterning also, memory elements which constitute a memory device is decreased in size, corresponding to which inter-word-line spacing is reduced, so that if such a small spacing between the word lines is employed in layout of a word-line driving circuit, that circuit has a poor layout efficiency of being long laterally, thus leading to a problem of a larger chip size.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a word-line driving circuit that can reduce the number of transistors which constitute a unit circuit, thus compacting a chip size of even a large scale semiconductor integrated circuit.
Also, it is an another object of the present invention to provide a semiconductor memory device having such a word-line driving circuit.
According to a first aspect of the present invention, there is provided a word-line driving circuit provided for each corresponding word line for selecting the predetermined word line with a low-order address signal from among a plurality of word lines divided into a plurality of blocks one of which is selected by a high-order address signal, the word-line driving circuit including:
a first P-channel type transistor connected between a first power supply for supplying a predetermined potential to selected word lines and a word line;
a second P-channel type transistor connected with the first P-channel type transistor in a flip-flop configuration;
a first N-channel type transistor which is connected between a first signal line for supplying a signal obtained by decoding a low-order address and a gate of the first P-channel type transistor and a gate of which is connected with a second signal line for supplying a signal obtained by decoding a high-order address;
a second N-channel type transistor which is connected between a second power supply for securing a potential of an unselected word line and the word line and a gate of which is connected with the first signal line; and
a third N-channel type transistor which is connected between the word line and the second power supply and a gate of which is connected with the second signal line.
In the foregoing, a preferable mode is one wherein the second power supply supplies a word line with a negative potential at a time of an erasure operation.
Also, a preferable mode is one wherein the second N-channel type transistor and the third N-channel type transistor both of which are connected to the second power supply are designed so as to be operative even when supplied with a negative potential.
Also, a preferable mode is one wherein the third N-channel type transistor is shared in use by two word-line driving circuits adjacent each other in the block and connected between word lines in the two word-line driving circuits and also a back gate of the third N-channel type transistor is connected with the second power supply.
Also, a preferable mode is one wherein the third N-channel type transistor is shared in use by two word-line driving circuit not adjacent to each other in the block and connected between the two word-line driving circuits and a back gate of the third N-channel type transistor is connected with the second power supply.
Also, a preferable mode is one wherein, when switching the word line from an unselected state to a selected state, the first power supply supplies a current to the word line in such a manner as to increase a potential of the word line up to a power-supply voltage, in response to switch-over of a signal obtained by decoding the low-order address signal; and
the first power supply is configured to supply a current to the word line in such a manner as to increase a potential of the word line to a step-up voltage higher than the power-supply voltage by a predetermined lapse of time elapses after completion of switch-over of the signal obtained by decoding the low-order address signal.
Also, a preferable mode is one wherein the predetermined lapse of time is a time lapse taken by the word line to reach a predetermined voltage after switch-over of the signal obtained by decoding the low-order address signal.
Also, a preferable mode is one wherein the predetermined voltage is 0.9 Vcc, where Vcc is a power-supply voltage.
Also, a preferable mode is one wherein the signal obtained by decoding the low-order address signal has been pulsed in response to a pulse signal which detected switch-over in an address signal for selecting a word line.
Furthermore, a preferable mode is one wherein the pulse signal is terminated in a predetermined lapse of time after detection of switch-over in an address signal for selecting a word line and, in a predetermined lapse of time after starting of the pulse signal, the first power supply supplies a step-up voltage higher than a power-supply voltage.
In a configuration of the above aspect, word lines are divided into a plurality of blocks so that from a block selected by high-order address signals, a predetermined word line may be selected by low-order address signals; with this, a word-line driving circuit comprises: two P-channel

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