Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-01-24
2002-04-09
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189090, C365S189110, C365S230060
Reexamination Certificate
active
06370063
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile memory device (hereinafter referred to as NVM), and more particularly, to a word line driver having a divided bias line in a NVM device and a method for driving word lines.
2. Description of the Related Art
In contemporary non-volatile memory (NVM) devices, a high voltage bias is supplied to a word line through a circuit referred to as “level shift” circuit, in a case where new predetermined data are to be programmed in a cell and previously programmed data are to be erased. In the NVM device, a supply voltage, or a voltage lower than the supply voltage, are supplied to the word line as a read bias through the same level shift circuit when data stored in a memory cell are read. For this reason, in conventional NVM device, the level shift circuit must be included to provide for the high voltage bias applied during programming/erase mode of operation.
Transistors forming the level shift circuit are generally comprised of transistors operated under a high voltage and therefore implemented by elements having larger sizes. As a result, the NVM device consumes additional circuit surface area. Further, during application of bias voltage in a read mode of operation, access time must also be considered, as a delay period can be incurred as the read bias voltage passes through the same level shift circuit and is transferred to the word line. Arising from these issues, since data read speed as well as operation voltage are considered as a function of the size of the level shift circuit transistors, they are therefore implemented by transistors having relatively larger channel widths. That is, in the NVM device, when the channel widths of the level shift circuit transistors are enlarged, considering the need for faster access speed and higher operation voltage, the corresponding transistor sizes may become larger, and the layout area of the overall memory device is likewise adversely enlarged.
In conclusion, in the conventional NVM device, in which the high voltage bias and the bias during the data read mode of operation are applied through the same level shift circuit, the access speed is reduced during the data read mode of operation, and the layout area of the memory device becomes greater.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a word line driver having divided bias line in a non-volatile memory (NVM) device, which is capable of improving access speed during a data read mode of operation without enlarging the layout size.
It is another object of the present invention to provide a method for driving word lines implemented in the word line driver in the non-volatile memory (NVM) device.
Accordingly, to achieve the first object, there is provided a word line driver in a non-volatile memory (NVM) device. The NVM device includes a row decoder for inputting and decoding a row address and outputting a word line select signal to select a word line in response to a decoded result, and a bias supply unit for generating a first voltage. The word line driver includes a plurality of level shift circuits and a plurality of switching devices. The plurality of level shift circuits shift the first voltage in response to an externally applied program/erase signal during a first mode of operation and output the shifted first voltage to the word line selected by the word line select signal. The plurality of switching devices are switched in response to the program/erase signal and transfer the word line select signal having a second voltage during a second mode of operation to the word line.
In order to achieve the second object of the present invention, there is provided a method for driving word lines implemented in a word line driver in a non-volatile memory (NVM) device. The NVM device includes a row decoder for decoding a row address and selecting a word line and a bias supply unit for generating a first voltage. The method for driving word lines comprises the steps of: a) determining whether a programming/erase mode of operation is performed; b) transferring the first voltage to the word line through a first data path when the programming/erase mode of operation is performed; c) determining whether a data read mode of operation is performed when the programming/erase mode of operation is not performed in the step a); and d) transferring a second voltage to the word line through a second data path when the data read mode of operation is performed in the step c).
REFERENCES:
patent: 5058063 (1991-10-01), Wada et al.
patent: 5852583 (1998-12-01), Taito et al.
patent: 6044020 (2000-03-01), Chung et al.
patent: 6128230 (2000-10-01), Amanai
patent: 6181606 (2001-01-01), Choi et al.
Mai Son
Mills & Onello LLP
Samsung Electronics Co,. Ltd.
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