Word line driver circuit for dynamic random access memories

Details Word line driver circuit for dynamic random access memories Word line driver circuit for dynamic random access memories

1991-02-05

1993-10-12

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

36523006, 365174, 36518911, 365149, H01L 2978, G11C 700

Patent

active

052532020

ABSTRACT:
A wordline driver circuit for reading the contents of a Dynamic Random Access Memory (DRAM). The circuit is implemented in CMOS and is capable of pulling the wordlines to a negative potential with respect to the substrate, thereby decreasing the access time. An NMOS pull-down transistor channel is implemented as a P-well within an N-well. Applying a negative potential to the source of the pull-down transistor permits the transistor to be switched so that a negative potential is applied to the wordline when the NMOS pull-down transistor is gated into conduction. A PMOS pull-up transistor is serially connected to the NMOS pull-down transistor drain, permitting the wordline to be driven positively.

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patent: 4720739 (1988-01-01), Bresom
patent: 4901280 (1990-02-01), Patel

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