Word line driver circuit for a static random access memory...

Details Word line driver circuit for a static random access memory... Word line driver circuit for a static random access memory...

2006-08-01

2006-08-01

Ho, Hoai V. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S225700, C365S230050

Reexamination Certificate

active

07085175

ABSTRACT:
A static random access memory (14) has a normal mode of operation and a low voltage mode of operation. A memory array (15) includes memory cells (16) coupled to a first power supply node (VDD) for receiving a power supply voltage. A plurality of word line drivers is coupled to word lines of the memory array (15) and to a second power supply node (37). A word line driver voltage reduction circuit (36) has an input coupled to the first power supply node (VDD) and an output coupled to the second power supply node (37) for reducing a voltage on the output in relation to a voltage on the input in response to a low power supply voltage signal, and thus improving a static noise margin of the memory cells (16).

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Bhavnagarwala et al., “Dynamic-Threshold CMOS SRAM Cells for Fast, Portable Applications,” IEEE, pp. 359-363 (2000).
Joshi et al., “Novel Circuits To Improve SRAM Performance in PD/SOI Technology,” 2001 IEEE International SOI Conference, pp. 99-100.
Itoh et al., “A Deep Sub-V, Single Power-Supply SRAM Cell with Multi-Vt, Boosted Storage Node and Dynamic Load,” IEEE 1996 Symposium on VLSI Circuits Digest of Technical Papers,pp. 132-133.

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