Word line driver circuit and method

Details Word line driver circuit and method Word line driver circuit and method

1993-09-27

1995-01-10

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518906, 326 89, 326105, G11C 1140

Patent

active

053813774

ABSTRACT:
A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of the driver circuits, each used to drive a word line in the memory array. The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pull up portion includes a pair of cascaded transistors arranged to pull up an output node coupled to the word line. The active pull down portion includes a pair of cascaded transistors arranged to pull down the output node coupled to the word line. A control feedback path is coupled between the output node and the active pull down portion of the driver circuit. The feedback path controls the activation of the pull down portion of the driver circuit.

REFERENCES:
patent: 4706222 (1987-11-01), Kwiatkowski et al.
"A 3.5 ns, 2 W, 20 mm.sup.2 16 Kb ECL Bipolar RAM" by K. Yamaguchi et al. 1986 IEEE International Solid-State Circuits Conf., pp. 214-215.
"A 23 ps/2.1 mW ECL Gate" by K. Toh et al., 1989 IEEE International Solid-State Circuits Conference, pp. 224-225.
"High Speed Low-Power Charge-Buffered Active Pull-Down ECL Circuit", by C. Chuang et al., Journal of Solid-State Circuits, May 1991.
"A 4-ns 4K X 1-bit Two-Port BiCMOS SRAM" by T. Yang et al., IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988.

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