Word line driver and semiconductor device

Static information storage and retrieval – Addressing – Particular decoder or driver circuit

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36523008, G11C 800

Patent

active

058869425

ABSTRACT:
A word line driver includes a CMOS inverter constituted by a P channel MOS transistor in which a row decode signal having the amplitude of an internal logic power supply voltage is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLh) is applied, and the other end of the source-drain current path is connected to a word line, and an N channel MOS transistor in which the input signal is supplied to a gate, one end of the source-drain current path is connected to a node to which a power supply voltage (VWLl) having a negative value is applied, and the other end of the source-drain current path is connected to the word line. The circuit threshold voltage of the CMOS inverter is set to be larger than the circuit threshold voltages of other CMOS inverters which operate using internal logic power supply voltages.

REFERENCES:
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patent: 5602796 (1997-02-01), Sugio
patent: 5617369 (1997-04-01), Tomishima et al.
patent: 5644548 (1997-07-01), Kitsukawa et al.
Yamagata et al., "Circuit Design Techniques for Low-Votage Operating and/or Giga-Scale DRAMs" ISSCC Dig. of Tech. Papers, pp. 248-249, 1995.

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