Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2001-01-25
2002-12-31
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Testing
C365S210130, C365S214000
Reexamination Certificate
active
06501691
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a burn-in test capability.
Because recent semiconductor memory devices, such as a DRAM (Dynamic Random Access Memory), are designed by extremely detailed design rules, DRAMs having an electrical deficiency, such as disconnection, are likely to be produced. To eliminate defects, a burn-in test is conducted on DRAMs before shipment. In the burn-in test, a voltage higher than the normal operational voltage is applied to elements in memory cells and lines over a predetermined time.
Since the conventional burn-in test performs a function operation to sequentially access the individual word lines after packaging, the burn-in test takes time. As the rate of shipping unpackaged chips as products increases, the burn-in test now takes place in the wafer test process.
In the normal operation of a DRAM, a single word line and a column are selected. Cell information is read from or written in those memory cells that are connected to the selected word line and column. In the burn-in test that is made in the wafer test process, a stress voltage is applied to selected plural word lines and bit lines for a predetermined time. This shortens the burn-in test time.
The publications that will be discussed below disclose semiconductor memory devices equipped with a burn-in test capability for selecting a plurality of word lines.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 6-60697 discloses a first prior art semiconductor memory device. The semiconductor memory device includes a row address selector connected to a memory cell array, a changeover circuit connected to the row address selector, a test mode detector connected to the changeover circuit and a refresh address generator connected to the changeover circuit. The refresh address generator supplies a refresh address signal to the changeover circuit. The test mode detector sends a burn-in-test-mode detection signal to the changeover circuit. In accordance with the level of the burn-in-test-mode detection signal, the changeover circuit sends an address select signal to the row address selector. At the time of a burn-in test, the burn-in-test-mode detection signal becomes active so that the changeover circuit supplies the row address selector with an address select signal to select all the word lines at a time.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 9-17199 discloses a second prior art semiconductor memory device. In this semiconductor memory device, the stress voltage is simultaneously supplied to all the word lines via transistors, which are connected to a plurality of word lines, in a burn-in test.
According to the first and second prior art devices, however, it is not detected whether the stress voltage has actually been applied to the word lines in the burn-in test. Since a plurality of memory cells are connected to each word line, each word line has a relatively long length of, for example, about 1000 &mgr;m. If a word line has a conductive failure, such as disconnection, the stress voltage is not applied to the word line over the entire length. Therefore, the burn-in tests according to the first and second prior art devices are relatively unreliable.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 5-67399 discloses a third prior art semiconductor memory device. In the burn-in test mode of the semiconductor memory device, the stress voltage is supplied to a measuring terminal from an external unit. The semiconductor memory device detects whether the stress voltage is supplied to the internal circuits. In the normal operation mode, on the other hand, the supply voltage is supplied to the measuring terminal. The semiconductor memory device detects whether the operational voltage is supplied to the internal circuits.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 9-147599 discloses a fourth prior art semiconductor memory device. The semiconductor memory device includes a burn-in circuit, which executes a burn-in test, an address key circuit, which supplies the burn-in circuit with a mode signal to instruct the execution of the burn-in test, and a burn-in-mode detector, which is connected to both the address key circuit and the burn-in circuit. The burn-in-mode detector detects whether the semiconductor memory device is in burn-in mode based on the mode signal and the input level of an external terminal signal.
In the third and fourth prior art devices, however, it is not detected whether the stress voltage has actually been applied to all the word lines.
Japanese Unexamined Patent Publication (KOKAI) No. Hei 5-282898 discloses a fifth prior art semiconductor memory device. The individual word lines of the semiconductor memory device are connected to the gates of MOS transistors. The current that flows between the drain and source of each transistor and the drain current that is originated from the ON action of the transistor are detected by a test terminal. This makes it possible to detect whether each word line is short-circuited with the power supply.
The transistors in the fifth prior art device are connected in a wired-OR fashion. When all the word lines are selected at a time in a burn-in test mode, therefore, the drain current simultaneously flows in a plurality of transistors. It is not therefore detected whether all the word lines have been selected properly.
As each transistor is turned on when the potential of each word line is equal to or higher than the source potential of that transistor by a predetermined value (threshold value), it is not detected whether the stress voltage has been applied to each word line. If the stress voltage applied to each word line is predictable based on the ON resistance of each transistor, it is not possible to estimate the ON resistance of each transistor when a plurality of transistors are selected at a time. Because the number of those word lines to which the stress voltage has not been applied adequately is not detected, it is not possible to determine whether the chip can be saved by the redundancy operation.
As apparent from the above, the reliabilities of the conventional burn-in tests are insufficient. To supplement the insufficient reliabilities, the wafer test process of semiconductor memory devices are carried out in the following fabrication process.
As shown in
FIG. 1
, a DC check on each chip on a wafer is performed first in step S
1
. The DC check sorts out defective chips with a large short-circuit current by detecting the short-circuit current with a supply voltage supplied to each chip. In step S
2
, a simple function check is performed on each chip on the wafer. The simple function check roughly checks the operation of the internal circuits of each chip.
In step S
3
, a wafer burn-in test is conducted. Then, a DC check in step S
4
and redundancy setting in step S
5
are carried out. In step S
6
, a full function check is executed to check whether all the memory cells operate normally by performing a write operation and read operation on all the memory cells.
In the case of manufacturing packaged devices, dicing (step S
7
), assembly (step S
8
) and a simple check (step S
9
) are executed. To supplement the reliability of the wafer burn-in test in step S
3
, an additional burn-in test is conducted in step S
10
through a normal operation of selecting the word lines one after another and applying the stress voltage to the selected word line. Then, a full function check is performed again (step S
11
) after which an assembled product will be shipped.
In the case of shipping device chips, an additional burn-in test is conducted on a wafer through the normal operation in step S
12
after step S
6
. Dicing is carried out after a DC check in step S
13
and a simple check in step S
14
, and device chips will then be shipped.
The additional burn-in tests (steps S
10
and S
12
) for improving the reliability of the burn-in test make the test time longer and the cost for the test higher.
SUMMARY OF
Kato Yoshiharu
Kawamoto Satoru
Mizutani Motoki
Nagai Shinji
Arent Fox Kintner & Plotkin & Kahn, PLLC
Elms Richard
Fujitsu Limited
Nguyen Van-Thu
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