Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Patent
1995-12-15
1998-01-06
Nelms, David C.
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
36523003, 365 63, G11C 700
Patent
active
057062455
ABSTRACT:
The present invention includes a plurality of memory cells store information and one row decoder for every four word lines to decode an external address output a single row decoding signal. A word drive decoder generates a word line driving signal. A split word line driver arranged such that the memory cell array is formed between each split word line driver, inputs the single row decoding signal output from the row decoder and the word line driving signal output from the word drive decoder to thereby output a word line signal to select appropriate memory cells. With this structure, the reduced number of metalized lines requiring straps which overlay the memory cell array help minimize short-circuit problems that would otherwise occur when dimensions of metalized lines are reduced.
REFERENCES:
patent: 4827449 (1989-05-01), Inoue
patent: 5140550 (1992-08-01), Miyaoka et al.
patent: 5214606 (1993-05-01), Hashimoto
patent: 5416748 (1995-05-01), Fujita
Noda, K. et al., "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113 (1992).
Le Vu A.
Nelms David C.
Samsung Electronics Co,. Ltd.
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