Word line decoding architecture in a flash memory

Details Word line decoding architecture in a flash memory Word line decoding architecture in a flash memory

2000-10-17

2002-02-12

Mai, Son (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S189090, C365S230060

Reexamination Certificate

active

06347052

ABSTRACT:

BACKGROUND
The present invention relates generally to semiconductor memory devices. More particularly, the present invention relates to decoding architectures in a flash memory.
Flash random access memory (RAM), more commonly known as flash memory, is a form of non-volatile storage that uses a memory cell design with a floating gate. High voltages are applied to the memory cell inputs to program or store charge on the floating gate or to erase or remove charge from the floating gate. Programming occurs by hot electron transfer to place charge on the floating gate while erasure makes use of Fowler-Nordheim tunneling in which electrons pierce a thin dielectric material, reducing the amount of electronic charge on the floating gate. Erasing a cell sets the logical value of the cell to “1” while programming the cell sets the logical value to “0”. Aside from programming or erasing operations, a flash memory operates similarly to a randomly accessible read only memory (ROM). Conventionally, a flash memory chip, including the flash memory storage cells and support logic/circuitry, is made by fabricating layers of semiconductor material and interconnect layers of polysilicon and first and second metal layers onto a substrate. It will be appreciated that there are numerous integrated circuit fabrication techniques, involving more or fewer layers, which are applicable herein.
In the design of integrated circuits, there is a trend to power the integrated circuits using decreasing power supply voltage levels. Previous circuit families operated at 5 volts and 3.3 volts. Current families operate at 1.8 volts and future families will operate at or below 1.0 volts nominal supply voltage, for example at 0.8 volts. These lower power supply voltages create design and operation challenges.
One design challenge relates to accessing a storage element or core cell of the memory device. The voltage swing available in low supply voltage systems such as a 1.8 volt supply system is typically insufficient for a read or a program of a flash memory cell. Accordingly, voltage boost circuits have been developed to provide the necessary voltage variation. For accessing the core cell, a word line voltage is boosted to, for example, 4.0 volts. This allows the core cell transistor to fully turn on and the core cell to sink enough current for rapid sensing of the state of the cell by the sensing circuitry. A high boosted voltage is generally required in a low supply voltage system such as a 1.8 volt supply system.
In order to boost the word line voltage for a particular word line, the word line is selected and a boosted voltage is supplied to the word line. Word line driver circuits are used to boost selected word lines to a boosted voltage. Word line driver circuits also provide final decoding of the row or X address of the selected core cell.
Typically, each word line has an accompanying word line driver circuit. With improvements in device layout and in process technologies, the core cells in a memory array are laid out at increasingly finer pitches. As word lines are placed closer together, limitations are placed on the size of the word line driver circuits. More recently, decoding schemes have been used to identify a particular word line driver circuit and an accompanying selected word line. The increased complexity of decoding schemes to access word line driver circuits and to supply boosted voltages to selected word lines has presented design challenges. In order to drive a word line, in many configurations voltage boost circuits and accessory circuitry face significant load capacitance at boosted nodes and driven nodes, impaired performance, and less than optimal word line selection times. It would be desirable to implement a more efficient decoding architecture in a flash memory that improves performance, reduces capacitive loading at boosted and driven nodes, and reduces word line selection times while being arranged to match the fine pitch of core cell array.


REFERENCES:
patent: 5511027 (1996-04-01), Shimizu
patent: 5781498 (1998-07-01), Suh
patent: 5808955 (1998-09-01), Hwang et al.
patent: 5875149 (1999-02-01), Oh et al.
patent: 6011746 (2000-01-01), Oh

Affiliated with

Also associated with

Rating

Word line decoding architecture in a flash memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Word line decoding architecture in a flash memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Word line decoding architecture in a flash memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2977809