Word line decoder/driver circuit and method

Details Word line decoder/driver circuit and method Word line decoder/driver circuit and method

1993-07-15

1995-03-28

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36523003, 326105, 326 84, G11C 1140

Patent

active

054023866

ABSTRACT:
A row select circuit for semiconductor memories is disclosed. The row select circuit includes a decoder portion and a driver portion. The decoder potion of the row select circuit includes a plurality of decoder circuits, each servicing a multiplicity of rows. Two levels of decoding are used to select a row. First, one of the plurality of decoder circuits is selected. Second, a predecoder is provided for simultaneously selecting one of the multiplicity of rows serviced by the selected decoder circuit. A single current source is used to service the multiplicity of rows associated with a particular decoder. The driver portion of the circuit includes a driver circuit for each row. Each driver includes an inverter stage, a driver stage, a clamp and a voltage reference circuit. For a selected row, the driver circuit provides ultra-fast access time. For the deselected rows, the driver circuit consumes minimal power.

REFERENCES:
patent: 4369503 (1983-01-01), Isogai
patent: 4730275 (1988-03-01), Baskett
patent: 5103113 (1992-04-01), Inui et al.
"An Experimental Soft-Error Immune 64-Kb 3ns ECL Bipolar RAM" by Yamaguchi et al., IEEE 1988 Bipolar Circuits & Technology Meeting.
"A 1.5-ns Access Time, 78-um.sup.2 Memory-Cell Size, 64-kb ECL-CMOS SRAM" by Yamaguchi et al., IEEE Journal of Solid-State Circuits.
"Bipolar and MOS Analog Integrated Circuit Design" by Alan B. Grebene, 1984.

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