Word line decoder

Details Word line decoder Word line decoder

2000-11-27

2002-05-14

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C326S105000, C365S230060

Reexamination Certificate

active

06388472

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to a word line. More particularly, the present invention relates to a word line in which the number of transistors constituting a word line decoder is reduced, thus reducing loading of boosting voltage and thus increasing reliability of a device.
BACKGROUND OF THE INVENTION
In order to perform read or write operation by selecting a specific cell in a flash memory cell, a corresponding cell is selected by word line and bit line select signals. Respective decoders are used to select these word line and bit lines.
Referring to
FIG. 1
, a circuit diagram of the conventional word line decoder will be explained below.
As can be seen from
FIG. 1
, a first PMOS transistor P
11
is connected between the power supply terminal and the first node Q
11
and is driven depending on a reset signal XRST. A second PMOS transistor P
12
is connected between a power supply terminal VPPX and a second mode Q
12
and is driven depending on the potential of an output terminal WL. A third PMOS transistor P
13
is connected between the power supply terminal VPPX and the output terminal WL and is driven depending on the potential of the second node Q
12
. A first NMOS transistor N
11
is connected between the first node Q
11
and the second node Q
12
, and the gate terminal of which is applies the power supply voltage so that it can be always kept turned on. A second NMOS transistor N
12
is connected between the first node Q
11
and a control signal input terminal XCOM and is driven depending on a decoder signal XPREA. A third NMOS transistor N
13
being a triple-well NMOS transistor is connected between the second power supply terminal VEEX and the output terminal WL and is driven depending on the power supply voltage Vcc and the second power supply terminal VEEX.
The conventional word line decoder as mentioned above is applied with different power supplies depending on program, erase and read operation. However, only the read operation will be explained below for simplicity.
In order to perform the read operation, the first power supply VPPX of the power supply voltage Vcc, the reset signal XRST of
0
V, the second power supply VEEX of
0
V, the decoder signal XPREA of the power supply voltage Vcc and the control signal XCOM of
0
V are applied. At this time, the output signal WL must be the power supply voltage Vcc.
The first PMOS transistor P
11
is turned on by the reset signal XRST to provide the first node Q
11
with the power supply voltage Vcc. However, as the second NMOS transistor N
12
is turned on by the decoder signal XPREA, and is thus applied with the control signal XCOM of a LOW state, the potential of the first node Q
11
is passed to the control signal input terminal. Therefore, the first node Q
11
maintains the potential of a LOW state. The potential of the first node Q
11
is passed to the second node Q
12
, through the first NMOS transistor N
11
always kept turned on since the gate terminal of which is applied with the power supply voltage Vcc. By means of the potential of the second node Q
12
kept at LOW state, the third PMOS transistor P
13
is turned on to provide the output terminal WL with the power supply voltage Vcc. As the output terminal WL is kept at the potential of the power supply voltage Vcc, the second PMOS transistor P
12
is turned off and the second node Q
12
is thus kept at LOW state. On the other hand, as the first node Q
11
is kept at LOW state, the third NMOS transistor N
13
is turned off and the third power supply VEEX is thus not supplied to the output terminal WL.
As mentioned above, the first power supply VPPX is directly transferred to operate the word line the word line decoder, depending on the reset signal XRST and the control signal XCOM.
In order to perform the above-mentioned operation, the conventional word line decoder employs six (6) transistors. However, in a situation where the number of decoders are required as many as the number of word lines, a lot of the transistors gives a significant burden on the chip size. Also, in a device that is driven with a low voltage, the boosting voltage must be applied to the word line. However, as the first power supply VPPX is applied to unselected word lines, loading by the boosting voltage will cause a serious problem.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a word line decoder capable of not only reducing the chip size but also solving the loading problem.
In order to accomplish the above object, a word line decoder according to the present invention is characterized in that wherein addresses for decoding word lines are divided into a global word line and a local word line, and if said global word line is selected, a voltage generated at said local word line is applied to a selected word line, but if said global word line is not selected, the voltage applied to said word line is passed to a ground terminal.


REFERENCES:
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patent: 5229967 (1993-07-01), Nogle et al.
patent: 5696721 (1997-12-01), McAdams et al.
patent: 5896340 (1999-04-01), Wong et al.
patent: 5986917 (1999-11-01), Lee
patent: 6031784 (2000-02-01), Ong
patent: 6064623 (2000-05-01), Ha
patent: 6233198 (2001-05-01), Choi
patent: 6278297 (2001-08-01), DeSoto et al.
patent: 6285593 (2001-09-01), Wong

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