Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
1999-08-02
2002-12-10
Ho, Hoai V. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S230060, C327S390000
Reexamination Certificate
active
06493276
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of voltage boost circuits. In particular, the invention relates to integrated circuits using word line boost circuits to produce on-chip voltages outside the range of the off-chip voltage supply.
2. Description of the Related Art
The electronics industry has continued to define standard power supply voltages of decreasing magnitudes. Decreasing power supply voltages, such as 5 volts, 3 volts, and 1.8 volts, raise the demands on modern circuits to provide sufficiently high on-chip voltages despite a lower off-chip supply voltage. Flash memory is an example of an application that would welcome more efficient boosting of a low off-chip supply voltage to an on-chip voltage sufficiently high to access flash memory cells. Therefore, what is needed is a word line boost circuit having higher boosting efficiency.
SUMMARY OF THE INVENTION
An improved word line boost circuit is disclosed that increases boosting efficiency. The improved word line boost circuit can be implemented in an integrated circuit that includes a memory array with word lines powered by word line drivers. Boosting efficiency is increased by floating a part of a first circuit that initially boosts an output voltage of the word line boost circuit. Floating part of the first circuit obviates the need for a diode to isolate the first circuit, and decreases the load on a second circuit that further boosts the output voltage of the word line boost circuit, thereby increasing efficiency.
A boost circuit includes an output, a precharge circuit connected to the output, a first capacitor with a first terminal connected to the output, a first circuit connected to a second terminal of the first capacitor, a second capacitor, and a second circuit connected to the output through the second capacitor. The second terminal of the first capacitor can be in a floating state, set to a first supply voltage, or a second supply voltage. An onset of a first boost operation performed by the first circuit is followed after a time delay by an onset of a second boost operation performed by the second circuit.
In some embodiments, one of the first supply voltage and the second supply voltage is a ground; the precharge circuit has a switching circuit connected to the output of the first voltage supply and the second voltage supply; and the second terminal of the first capacitor switches between i) a floating state, ii) being set to a first supply voltage, and iii) being set to a second supply voltage in response to one or both of a first signal and a second signal.
In a further embodiment, the word line boost circuit is part of an integrated circuit device with a substrate. In yet another embodiment, the word line boost circuit is part of an integrated circuit memory device with a substrate, a memory array, and word lines.
A method for reducing energy consumption of a boost circuit to achieve higher boosting efficiency for the above mentioned word line boost circuit comprises: precharging an output to a precharge voltage, changing the output to a first voltage with a first coupling circuit that is connected to the output, floating a part of the first coupling circuit, and changing the output to a second voltage with a second coupling circuit connected to the output.
In some embodiments, the method for reducing energy consumption of a boost circuit to achieve higher boosting efficiency for the above mentioned word line boost circuit comprises: changing an output from a precharge voltage to a first voltage with a first circuit, setting a node in the first circuit to a floating voltage, and changing the output from the first voltage to a second voltage with an energy expenditure that is lower than if the node were not floating.
REFERENCES:
patent: 4769792 (1988-09-01), Nogami et al.
patent: 5612924 (1997-03-01), Miyamoto
patent: 5701096 (1997-12-01), Higashiho
patent: 5708387 (1998-01-01), Cleveland et al.
Hung Chun-Hsiung
Lin Yu Shen
Wan Ray-Lin
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Ho Hoai V.
Macronix International Co. Ltd.
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