Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-09-26
2004-12-14
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S637000
Reexamination Certificate
active
06831009
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to wiring substrates; and, more particularly, the invention relates to a multilayer wiring substrate comprising a copper layer formed at a fine or “micro” opening such as via-hole, for interconnection between a plurality of wiring leads, to a method of manufacture thereof, and to an electroless copper plating solution used in the method.
Currently available electroless copper plating solutions contain copper ions, a complexing agent of copper ions, a reducing agent of the copper ions, and a pH adjuster. Such solutions further contain an additive agent mixed thereinto for purposes of improving the mechanical characteristics of a plated film(s) or, alternatively, for improving the stability of the plating solution.
One typical electroless copper plating solution containing these additive agents is disclosed, for example, in JP-A-51-105932 (1976). The plating solution taught by this Japanese document contains, as its additive agents, at least one of 2,2′-bipyridyl, 2-(2-pyridyl)benzimidazole and 2,2′-diquinolyl; at least one of polyalkylene glycol and/or 1,10-phenanthroline group; and polyalkylene glycol.
JP-A-52-17334 (1977)) discloses an electroless copper plating solution containing, as an additive agent, at least one of murexide, eriochrome black T, and methyl violet.
JP-A-52-17335 (1977) discloses an electroless copper plating solution containing, as an additive agent, at least one material selected from the group consisting of pyridine, 4-vinylpyridine, 2-aminopyridine, 2-methylpyridine, 3-methylpyridine-4-methylpyridine, 2-ethylpyridine, 3-(n-propyl)pyridine, and 2-hydroxypyridine.
JP-A-52-20339 (1977) teaches an electroless copper plating solution containing, as additive agents, at least one of metal salts of Ni, Co, Pb and Sn, and also a nonreactive aliphatic group polymer.
JP-A-52-21226 (1977) discloses an electroless copper plating solution containing more than one of the materials selected from the group consisting of allyl alcohol, &agr;-chloro-allyl alcohol, &bgr;-chloroallyl alcohol, &agr;-methylallyl alcohol, and &bgr;-methylallyl alcohol.
Furthermore, JP-A-52-85936 (1977) discloses an electroless copper plating solution containing oxime as an additive agent. JP-A-56-105468 (1981) discloses an electroless copper plating solution containing, as additive agents, polyethylene glycol stearylamine, 2,2′-bipyridyl, and Ag
2
S. JP-A-57-26156 (1982) discloses an electroless copper plating solution with cyclic polyether added as its additive agent. JP-A-5-156459 (1993) teaches an electroless copper plating solution to which iodine compounds and 2,2′-bipyridyl are added.
Any one of the additive agents stated above can be used for the purpose of improving the mechanical characteristics of a plated film and/or the stabilities of a plating solution in which it is used. In recent years, the quest for further miniaturization or “downsizing” in electronic equipment has resulted in parts-mounting substrates being under strict requirements for achievement of higher integration densities. To meet such needs, built-up substrates offering high-integration mountability have been vigorously studied and developed by many engineers to date. Build-up substrates are typically designed to employ a via-hole structure using through-going holes that are selectively formed only at necessary interlayer portions for electrical interconnection, rather than traditional through-hole interconnection schemes using interlayer connection structures, as in conventional printed circuit boards.
With the increase in the integration densities, such via-holes decrease in diameter, resulting in an increase in the aspect ratios of via-holes to be connected by metal plating processes. In cases where plating is applied to one-side closed via-holes for achievement of an intended electrical interlayer connection, it becomes more difficult to uniformly perform metal plating within such via-holes with an increase in via-hole aspect ratios. This difficulty might often serve as a serious bar or “process bottle-neck” in the manufacture of highly integrated parts-mount substrates.
In brief, a need is felt to develop a specific technique for coating, with good reproducibility, a copper layer of uniform thickness on or over the surface of a “closed” bottom portion and/or the surface of a sidewall within an opening with large aspect ratios, wherein the film is substantially the same in thickness as a copper layer being coated on or over an upper surface.
It is therefore a primary object of the present invention to provide a new and improved wiring substrate that is capable of offering enhanced parts mountability with high integration densities.
It is another object of this invention to provide an improved multilayer wiring substrate with high-integration parts mountability, including a metal-plated wiring layer as formed at one-side closed ultrafine via-holes of high aspect ratios.
It is yet another object of the invention to provide an improved electroless copper plating solution that has excellent uniformity of deposition properties of a copper layer relative to such via-holes.
SUMMARY OF THE INVENTION
A summary of some representative principal concepts of the invention as disclosed herein will be set forth below.
Firstly, an electroless copper plating solution in accordance with the instant invention that has excellent copper layer deposition uniformity is specifically arranged to contain therein copper ions, a complexing agent of such copper ions plus a reducing agent of these ions, as well as a “pH” adjuster, with at least one of mandelonitrile and triethyltetramine being added thereto as an additive agent.
Another electroless copper plating solution in accordance with the invention that has excellent copper layer deposition uniformity is arranged to contain a copper ion, a complexing agent of the copper ion, a copper ion reducing agent, a pH adjuster and an additive agent of at least one of 2,2′-bipyridyl, 1,10-phenanthroline and 2,9-dimethyl-1,10-phenanthroline, wherein at least one of mandelonitrile, triethyltetramine and eriochrome black T is further added as additive agent.
The intended multilayer wiring substrate preferably embodying the invention with a wiring layer formed through uniform plating at more than one ultrafine or “micro” via-hole of high aspect ratio is manufacturable with increased reproducibility through electroless copper plating processes using the specific plating solution stated supra.
Practically, the above-noted electroless copper plating solution is used to apply electroless copper plating to a wiring structure which includes more than one opening having on a dielectric body surface an ultrafine diameter &phgr; ranging from 50 to 150 &mgr;m and a closed bottom portion deeper than such diameter, i.e. whose depth is greater In value than its width, thereby enabling fabrication of a continuous copper layer with an almost uniform thickness on or over sidewall and bottom surfaces within the opening and the dielectric body surface. This in turn makes it possible to manufacture with good reproducibility the intended wiring substrate wherein the thickness of a copper layer on the sidewall/bottom surfaces within the micro-opening of aspect ratios ranging from 1.0 to 2.0 is greater than 0.9 times that of a copper layer overlying the dielectric body surface.
A further feature of the invention lies in an ability to provide, with increased reproducibility, a multilayer wiring substrate having a microfabricated high-density wiring structure, by application to an opening having a substantially perpendicular cross-section or profile having a specified angle &bgr; which the sidewall surface within the opening forms with the dielectric body surface, wherein the angle falls within a range of from 90 to 100 degrees.
REFERENCES:
patent: 3645749 (1972-02-01), Paunovic
patent: 4099974 (1978-07-01), Morishita et al.
patent: 6290825 (2001-09-01), Fu
patent: 6326559 (2001-12-01), Yoshioka et al.
patent: 0 964 610 (19
Akahoshi Haruo
Iida Tadashi
Itabashi Takeyuki
Nishimura Naoki
Takai Eiji
Antonelli Terry Stout & Kraus LLP
Le Dung A.
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