Wiring structure of thin film transistor array and method of man

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

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Details

257774, 257776, H01L 2348, H01L 2352, H01L 2940

Patent

active

06011309&

ABSTRACT:
The present invention relates to a method for connecting the two conductive lines located on separate layers with an intervening insulation layer between them, and a wiring structure formed by the same method. The method includes the steps of forming a first conductive layer on the substrate, forming an insulation layer on the first conductive layer, forming a second conductive layer having a first portion overlapping the first conductive layer, removing a portion of the first portion of the second conductive layer that overlaps the first conductive layer to form a top contact hole exposing a portion of the insulation layer, removing the exposed portion of the insulation layer through the top contact hole to form an enlarged contact hole, and forming a conductive pad in contact with the first conductive layer and the second conductive layer through the enlarged contact hole.

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patent: 5204286 (1993-04-01), Doan
patent: 5229645 (1993-07-01), Nakashima
patent: 5442236 (1995-08-01), Fukazawa
patent: 5512778 (1996-04-01), Chung et al.
patent: 5684331 (1997-11-01), Jun
patent: 5691572 (1997-11-01), Chung
patent: 5739579 (1998-04-01), Chiang et al.
patent: 5760429 (1998-06-01), Yano et al.

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