Wiring structure for semiconductor element and method for formin

Details Wiring structure for semiconductor element and method for formin Wiring structure for semiconductor element and method for formin

1998-04-06

1999-11-30

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Physical configuration of semiconductor

With electrical contact in hole in semiconductor

257663, 257774, 257502, 257503, 438620, 438612, 438613, H01L 2940

Patent

active

059947632

ABSTRACT:
A wiring groove 5 and a via-hole 7 (9) is formed on the backside surface 3 of a semiconductor chip 1. A circuit electrode ER led from the circuit formed on the chip 1 and a boding pad BP, both of which are formed on the front surface of the semiconductor element, are electrically connected with each other with the help of a backside wiring formed in the wiring groove 5 and a penetration wiring 13 formed in the via-hole 7 (9). With such a wiring structure, it is made possible to form a wiring pattern using the wire having an adequate width, without increasing the size of the semiconductor chip 1.

REFERENCES:
patent: 4286374 (1981-09-01), Hantusch
patent: 5037782 (1991-08-01), Nakamura et al.
Wu, "IBM Technical Disclosure Bulletin", vol. 16 No. 9, pp. 2898-2899, Feb. 1974.

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