Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-28
2003-06-03
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06574785
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a wiring method for a semiconductor integrated circuit with reduced noise and a computer product.
BACKGROUND OF THE INVENTION
FIG. 21
is a layout diagram of an example of a conventional semiconductor integrated circuit. This semiconductor integrated circuit includes elements
81
,
82
and
83
, a signal line
84
connecting the elements
81
and
83
with each other, and a signal line
85
connecting the elements
82
and
83
with each other. A predetermined standard for time operation guarantee and the like is prescribed for a time gap between a rise time or fall time of a signal that flows through the signal line
84
and a rise time or fall time of a signal that flows through the signal line
85
. The signal lines
84
and
85
are kept as short as possible in order to easily achieve this standard.
FIG. 22
is a timing chart showing one example of signals that flow through the conventional signal lines
84
and
85
. It is assumed, for example, that there is a prescribed standard of a
51
sec as a gap between a timing that a signal A
51
that flows through the signal line
84
rises from a low level to a high level and a timing that a signal B
51
that flows through the signal line
85
rises from a low level to a high level. Since the signal lines
84
and
85
are wired as short as possible, the signals A
51
and B
51
rise steeply. Therefore, a time gap b
51
sec between the rise time of the signal line A
51
and the rise time of the signal line B
51
becomes sufficiently small in comparison to the standard time gap a
51
sec.
FIG. 23
is a timing chart showing another example of signals that flow through the conventional signal lines
84
and
85
. It is assumed, for example, that there is a prescribed standard of a
52
sec as a gap between a timing that a signal A
52
that flows through the signal line
84
falls from a high level to a low level and a timing that a signal B
52
that flows through the signal line
85
falls from a high level to a low level. Since the signal lines
84
and
85
are wired as short as possible, the signals A
52
and B
52
fall steeply. Therefore, a time gap b
52
sec between the fall time of the signal line A
52
and the fall time of the signal line B
52
becomes sufficiently small as compared to the standard time gap of a
52
sec.
FIG. 24
is a timing chart showing still another example of signals that flow through the conventional signal lines
84
and
85
. It is assumed, for example, that there is a prescribed standard of a
53
sec as a gap between a timing that a signal A
53
that flows through the signal line
84
rises from a low level to a high level and a timing that a signal B
53
that flows through the signal line
85
falls from a high level to a low level. Since the signal lines
84
and
85
are wired as short as possible, the signals A
53
and B
53
fall steeply. Therefore, a time gap b
53
sec between the rise time of the signal line A
53
and the fall time of the signal line B
53
becomes sufficiently small as compared to the standard time gap of a
53
sec.
According to the above prior-art techniques, the signal lines are wired as short as possible. As a consequence, the signals rise and fall steeply. When the signals rise and fall steeply like this, there is a drawback that overshoot or undershoot is generated which results into an increase in the noise.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a wiring method for a semiconductor integrated circuit with reduced noise by suppressing occurrences of overshoot and undershoot, and a computer-readable recording medium storing a program for making the computer execute this method.
In the wiring method for a semiconductor integrated circuit according to one aspect of the present invention, signal lines are wired to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
In the wiring method for a semiconductor integrated circuit according to another aspect of the present invention, the lengths of signal lines are extended to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
In the wiring method for a semiconductor integrated circuit according to still another aspect of the present invention, the widths of signal lines are expanded to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
In the wiring method for a semiconductor integrated circuit according to still another aspect of the present invention, one or a plurality of through-holes are provided on signal lines to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
In the wiring method for a semiconductor integrated circuit according to still another aspect of the present invention, signal lines are branched to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
In the wiring method for a semiconductor integrated circuit according to still another aspect of the present invention, signal lines are provided with one or a plurality of parallel routes to maximize a gap in timing between the signal lines within a predetermined standard, thereby slowing a rise and a fall of signals.
A computer-readable recording medium according to still another aspect of the present invention is recorded with a program for making the computer execute any one of the above methods relating to the invention. With this arrangement, it is possible to make the computer execute the methods of the above-described methods relating to the invention.
In this case, the “computer-readable recording medium” includes a “portable physical medium” such as a magnetic disk like a floppy disk, a semiconductor memory (including that incorporated in a cartridge or a PC card) like a ROM, an EPROM, an EEPROM, a flash ROM, etc., an optical disk like a CD-ROM, a DVD, etc., an optical magnetic disk like an MO, etc., and a “fixed physical medium” like a ROM, a RAM, a hard disk, etc. that are incorporated in various types of computer systems.
Further, the “computer-readable recording medium” may also include a communication medium for short-time holding a program like a communication line for transmitting a program via a network like a LAN, a WAN, Internet, etc. The “program” is a one that describes a data processing method. A language to be described and a describing method are not particularly limited, and formats of a source code, a binary code and an execution format are not limited. Further, the “program” is not necessarily limited to a one formed in a single structure, but also includes a distributed structure as a plurality of modules and libraries, and a program that achieves its function in co-operation with separate programs of an OS and the like.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.
REFERENCES:
patent: 5550748 (1996-08-01), Xiong
patent: 5798656 (1998-08-01), Kean
patent: 5923676 (1999-07-01), Sunter et al.
patent: 6316958 (2001-11-01), Jenkins, IV
patent: 63-87744 (1988-04-01), None
patent: 4-137652 (1992-05-01), None
patent: 6-223134 (1994-08-01), None
Do Thuan
Leydig , Voit & Mayer, Ltd.
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
LandOfFree
Wiring method for semiconductor integrated circuit and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wiring method for semiconductor integrated circuit and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring method for semiconductor integrated circuit and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3145893