Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-10-05
2002-09-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S107000, C438S455000, C438S622000
Reexamination Certificate
active
06448174
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
N/A
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
N/A
BACKGROUND OF THE INVENTION
This invention concerns a wiring method for producing a vertical integrated circuit structure. More specifically, the invention concerns a wiring method for vertical system integration.
A method for producing a vertical integrated circuit structure is known from German unexamined patent application DE 44 38 846 A1. In that method, first of all, the individual layers of components are processed on different substrates, independent of one another, and then joined together. First, via holes that go through all existing layers of the components are opened on the front of the top substrate. After that, the top substrate is thinned from the back as far as the via holes. Then, a finished bottom substrate is connected to the top substrate. After that, the via holes are extended as far as the metallization level on the bottom substrate (so-called interchip via holes), and, by filling the via hole with metallic material and structuring the metallic material on the surface of the chip stack so there is a connection between the via hole and the contact area on the uppermost metallization level, the contact between the top and bottom substrate is created (wiring).
The disadvantage of this method is, however, the fact that the integration density is not satisfactory.
The goal of this invention is therefore to provide a CMOS-compatible method for vertical system integration with freely selectable vertical contacts located between circuit structures of layers of components that have been joined together, which makes high integration density and low production costs possible. The goal of the invention is also to provide a vertical, integrated circuit structure with high integration density that can be produced simply.
This invention creates a wiring method for: producing a vertical integrated-circuit structure, with steps for providing a first substrate, which contains, in the first main area, one or more initial layers with circuit structures, and at least one uppermost metallization level with contact areas; opening via holes, in a first step, in the first main area of the first substrate; providing a second substrate, which contains, in the second main area, at least one layer with circuit structures and at least one metallization level; connecting the first substrate to the second substrate, so that the side of the first substrate opposite the first main area, and the side of the second main area of the second substrate are joined together in alignment; opening the existing via holes up to a predetermined metallization level of the second substrate; producing an electrically conductive connection between the first metallization level of the first substrate and the predetermined metallization level of the second substrate, so that via holes are opened in such a way that the via holes abut the contact areas of the uppermost metallization level of the first substrate.
This invention also creates a wiring method for producing a vertical integrated-circuit structure with steps for providing a first substrate that contains, in the first main area, one or more initial layers with circuit structures, and whose uppermost metallization level is not completed; for opening via holes in a first step in the first main area of the first substrate; for providing a second substrate that contains, in the second main area, at least one layer with circuit structures, and at least one metallizing layer; for connecting the first substrate to the second substrate, so that the side of the first substrate opposite that of the first main area and the side of the second main area of the second substrate are joined together in alignment; in a second step, opening the existing via holes as far as a predetermined metallization level of the second substrate; inserting a metallic material into the via holes; and selective metallization of the surface, as a result of which an uppermost metallization level of the first substrate is brought into contact with the predetermined metallization level of the second substrate by means of the metallic material in the via holes, in the course of which, the via holes are opened in such a way that the via holes abut the contact areas of the uppermost metallization level provided.
In the method in the invention, the individual layers of components are processed independent of each other on different substrates and then joined together. First of all, the substrate that has been finish-processed (the first substrate, hereinafter referred to as the top substrate), is equipped, at those points along the front with one or more layers of components and metallization levels, whose layers of structural elements, in the finished, vertically integrated microelectronic system, will be above the layers of the components of an additional substrate (second substrate, hereinafter referred to as the bottom substrate), with via holes at those points on the front at which vertical contact with the layers of components on the bottom substrate, which are under it, will be produced later.
The method differs from the state of the art known in unexamined patent application DE 44 38 846 A1, in that in the invention, the via holes penetrate structures of the uppermost metallization level. Preferably, they also penetrate all layers of components and metallization levels present in the top substrate. The via holes preferably end a few micrometers beneath the layers of the components on the top substrate, when an SOI substrate is used, preferably at the buried oxide layer. If the etching technique used here and later makes it necessary, the top substrate can be equipped with a so-called hard mask before the via holes are produced.
After the via holes are opened, the top substrate can be thinned from the back. Thinning can be done by wet chemical etching, and/or by mechanical, and/or by chemical-mechanical grinding, for example, so that, if necessary, the top substrate is mechanically stabilized with an auxiliary substrate applied to the front by means of an adhesive layer (handling substrate). In the process, the adhesive layer can have a passivating and/or planarizing function. However, thinning can also be done without using a handling substrate. For example, using current techniques, it is possible to thin the top substrate to a residual thickness of up to 50 &mgr;m without using the handling substrate.
When using an SOI substrate, the buried layer of insulation can serve to good advantage as an etching stop during thinning. When using a conventional substrate (made of so-called bulk material), thinning can be done up to the via holes, so that afterward, they are open toward both sides of the top substrate.
Alternatively, it is naturally also possible to use a thin top substrate a priori, so there is no need for more thinning.
Then, another finish-processed substrate with one or more layers of components and metallization levels, the bottom substrate, is connected to the top substrate. For this, without imposing limitations in any general way, the front of the bottom substrate and/or the back of the top substrate can be equipped with a transparent adhesive layer. The adhesive layer can simultaneously perform a passivating and/or planarizing function. Then the top substrate and the bottom substrate are aligned to one another, and the back of the top substrate is connected to the front of the bottom substrate.
It is an advantage if alignment is done with split optics using alignment marks in the visible spectral range. Preferably, the alignment marks are made on the top substrate like the via holes by opening corresponding alignment structures from the front through all component layers of the top substrate. The alignment marks on the bottom substrate can be contained in the uppermost metallization level of the bottom substrate.
After the top and bottom substrate are joined together, the handling substrate that was used is removed, if necessary.
The existing stack of substr
Fraunhofer-Gesellschaft Zur Forderung der Angewandten Forschung
Niebling John F.
Simkovic Viktor
Weingarten Schurgin, Gagnebin & Lebovici LLP
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