Wiring layout method of integrated circuit

Details Wiring layout method of integrated circuit Wiring layout method of integrated circuit

2005-05-10

2005-05-10

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06892372

ABSTRACT:
A wiring layout method of an integrated circuit is disclosed. Checking of wiring area ratio is performed after an automatic wiring process. For a wiring other than a grid-shaped wiring, the line width W is classified into three steps of line-width range, and a minimum space width Smin between lines in each step of line-width range is defined in advance to satisfy a condition that Wmax/(Wmax+Smin)≦Pmax for a maximum line width Wmax in each step of line-width range. For grid-shaped wirings, a line width W is classified into two steps of line-width range. Further, in its upper step of line-width range, an allowable minimum area Amin (Amin≧Amin0) of a metal-removed area A is defined in advance to satisfy a condition that the wiring area ratio P is less than the allowable maximum value Pmax for a maximum line width Wmax. On the other hand, in its lower step of line-width range, made is a definition that the wiring area ratio P is same as the allowable maximum value Pmax for a maximum line width Wmax. Layout of wirings whose space width or metal-removed area has been checked not to satisfy the definitions is corrected in order to satisfy them.

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