Wiring layout apparatus, wiring layout method, and wiring...

Details Wiring layout apparatus, wiring layout method, and wiring... Wiring layout apparatus, wiring layout method, and wiring...

2007-04-11

2010-06-08

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

07735043

ABSTRACT:
A wiring layout apparatus includes a layout design unit configured to design a wiring layout for a semiconductor integrated circuit; a critical wiring detection unit configured to analyze a delay of signal propagation in the wiring layout so as to detect wiring strip conductors that configure a signal path whose timing is critical; a rewiring unit configured to rearrange the wiring strip conductors so as to improve the uniformity of a wiring pattern of an area in the vicinity of the critical wiring strip conductor, with regard to the wiring layout; and a strip-conductor-size variation determination unit configured to evaluate the uniformity of the pattern of the rearranged wiring layout so as to determine whether or not variation in the size of the critical wiring strip conductor falls within a tolerance range.

REFERENCES:
patent: 5638292 (1997-06-01), Ueda
patent: 6990597 (2006-01-01), Abe et al.
patent: 7331027 (2008-02-01), Meaney
patent: 7392496 (2008-06-01), Schultz et al.
patent: 2003308351 (2003-10-01), None
Machine translation of JP 2003308351 A using http://www19.ipdl.inpit.go.jp/PA1/cgi-bin/PA1INIT?1176720631969.

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