Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-10
2003-12-09
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C438S612000, C438S006000
Reexamination Certificate
active
06662351
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a wiring editing method, for a semiconductor package and using a CAD system, for correcting the offset of a wiring pattern passing between vias by arranging a pad to be connected to a semiconductor chip, and vias around the pad, on a virtual plane and describing a wiring pattern for connecting the pad and the vias.
2. Description of the Related Art
When wiring patterns of a semiconductor package such as a PBGA (Plastic Ball Grid Array) or an EBGA (Enhanced Ball Grid Array) are designed by use of a CAD system, design is done so that pads (such as wire bonding pads) electrically connected to electrode terminals (called “chip pads”) of the semiconductor chip and vias (lands) disposed round the former can be connected, or the vias can be connected with one another, on the virtual plane.
An ordinary procedure of designing wiring for a semiconductor package will be explained.
Wiring design is done for each layer when a substrate (circuit board) of a semiconductor package has single-layered wiring or multi-layered wiring. More concretely, the procedure is explained as follows.
First, a designer determines an outline of a semiconductor package and the arrangement of solder balls to serve as connection terminals on a virtual plane by use of the CAD system.
Next, an outline of a die pad for mounting the semiconductor chip is formed, and the bonding pads are arranged around the die pad in an arbitrary shape such as a linear shape, a zigzag shape or a circular arc shape.
The bonding pads and the chip pads of the semiconductor chip are connected. (This connection includes not only wire-bonding connection but also flip-chip connection).
Wiring is then done, while a wiring route is determined, lead wires from the bonding pads to the other bonding pads, from via-hole plating portions to the other via-hole plating portions and from the bonding pads to the via-hole plating portions cross one another. At this time, lines and spaces between the via-hole plating portions are calculated and the wiring route is so decided as to satisfy a design rule. Wiring is done from all the bonding pads. A re-design of the wiring is sometimes necessary so as to correct offset of wiring and the via positions.
A so-called “Even Space Method” is a method that was developed to efficiently produce a wiring design for a semiconductor package. This method conducts automatic wiring by means of circular arcs and line segments on a virtual plane by use of the CAD system, and then increases the width of the line segments or makes uniform the wiring gaps (lines and spaces) between the vias, to a certain extent.
According to this method, concentric circles are equidistantly drawn around a via, for example, and a tangent is drawn between specific concentric circles to automatically determine the wiring route between the adjacent vias. Thereafter, an offset of the wiring, and its concentration, resulting from this automatic wiring are corrected.
Even though the designer corrects the wiring gap and offset of the positions of the vias (lands) after provisionally wiring the bonding pads and the vias (lands), changes to the wiring positions are substantially difficult because the positions of the vias cannot be changed unconditionally. The design itself must be reduce once again in some cases.
Simultaneous decision of the wiring route, simultaneously with checking as to whether or not the wiring gap is in conformity with the design rule, renders the system more complicated. In this case, the system cannot be easily expanded or changed, and a satisfactory wiring result cannot be obtained easily.
The Even Spaced method is relatively effective when the vias (lands) formed on the substrate of the semiconductor package are formed regularly and equidistantly. In practice, however, they are formed in an irregular arrangement. Particularly when an excessive space is formed around a via, wiring becomes redundant or an offset is likely to occur in the wiring.
In this case, it becomes necessary to increase the radii of the concentric circles of the vias, at which the gaps between lead wires are small, for re-wiring, or to cut the circular arc and to again join the lead wires, or to move the lead wires. Such a correction step causes much trouble, cannot reflect the merit of automatic wiring and is likely to wrongly connect the lead wires.
When a large number of circular arcs are used, the editing on the CAD system requires a long time. When the wiring gaps are small, for example, it is necessary to increase the radii of the concentric circles of the vias for re-wiring, or to cut the circular arc and to again join the lead wires, or to move the lead wires. When the correction width is not uniform, the correction step is time-consuming, the merit of automatic wiring cannot be reflected, and a mistake in the wiring is likely to occur.
When a photo etching mask is directly produced on the basis of the circular arc, the processing time becomes twice or three times longer than that of the line segment.
It is an object of the present invention to provide a wiring editing method for a semiconductor package that solves the problems of the prior art technologies described above, forms each wiring pattern passing between vias as line segments and thus can easily edit an offset in the wiring pattern.
SUMMARY OF THE INVENTION
To accomplish the object described above, the present invention employs the following means.
Namely, the present invention provides a wiring editing method for a semiconductor package, using a CAD system, by arranging pads connected to a semiconductor chip and vias around the pads on a virtual plane, by drawing a wiring pattern for connecting the pads and the vias and correcting the offset of the wiring pattern passing between the vias, comprising the steps of:
assuming virtual circular arcs, considering the clearance around a predetermined one of the vias, inside a designated area on the virtual plane;
drawing a regular polygon circumscribing each of the virtual circular arcs; and
when the virtual circular arcs cross any of the vias, drawing a tangent from the crossed vias to the crossing virtual circular arc and connecting said regular polygon circumscribing the crossing circular arc to form a wiring pattern.
The wiring editing method of the present invention is also characterized in that each side of the regular polygon crosses at a right angle, a line segment connecting the via positioned at the center of the virtual circular arcs and each of the vias arranged around the center via part.
REFERENCES:
patent: 6121063 (2000-09-01), Liu et al.
patent: 6226560 (2001-05-01), Hama et al.
patent: 6298473 (2001-10-01), Ono et al.
patent: 2002/0028573 (2002-03-01), Kitamura et al.
patent: 10-214898 (1998-08-01), None
Ichimura Takahide
Kitamura Tamotsu
Nagasaki Takayuki
Sakai Hiroyuki
Lin Sun James
Paul & Paul
Shinko Electric Industries Co. Ltd.
Siek Vuthe
LandOfFree
Wiring editing method, for semiconductor package, capable of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wiring editing method, for semiconductor package, capable of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wiring editing method, for semiconductor package, capable of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3168927