Wiring diagram verifying method, program, and apparatus

Details Wiring diagram verifying method, program, and apparatus Wiring diagram verifying method, program, and apparatus

2006-07-04

2006-07-04

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07073142

ABSTRACT:
A layer defining unit defines different layer numbers to oblique wiring diagrams and via cell diagrams which are included in layout data of a semiconductor integrated circuit design. A first diagram blending unit fetches diagram data including the oblique wiring diagrams and the via cell diagrams from the layout data, synthesizes the diagrams every same layer number, and blends them in overlapped portions. An oblique wiring verifying unit verifies an interval between the oblique wiring diagrams blended by the first diagram blending unit by an allowable minimum interval value S. A second diagram blending unit synthesizes the verified oblique wiring diagram and the via mat diagram of the via cell, thereby forming an oblique wiring mask diagram blended in an overlapped portion. A blended diagram verifying unit verifies an interval between the oblique wirings having projecting portions by the via cells of the oblique wiring mask diagram blended by the second diagram blending unit by an allowable minimum interval value T (where, T<S).

REFERENCES:
patent: 6606731 (2003-08-01), Baum et al.
patent: 2887881 (1990-11-01), None
patent: 4205382 (1992-07-01), None
patent: 11297831 (1999-10-01), None

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