Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-03
2003-04-08
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C257S208000
Reexamination Certificate
active
06546537
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring data generation method such as of a clock line layout in a hierarchical layout, and particularly to a wiring data generation method that allows flexible block arrangement adjustment at the LSI (Large Scale Integrated circuit) level, and an apparatus therefor.
2. Description of the Background Art
It is difficult to properly supply a clock simultaneously to all the sequential elements in an LSI. Time difference occurs among the clocks supplied to each unit. This time difference is called “clock skew”. Particularly as the LSI is increased in integration density and the circuit scale becomes larger, the clock skew to the units in the LSI must be suppressed as low as possible. How the clock skew is reduced is of great concern. Since the clock skew is generated mainly at the design stage, skew control of high accuracy is required in configuring the clock.
A conventional skew control method is described hereinafter with reference to
FIGS. 1A and 1B
. A clock signal supplied to an LSI
221
from an input CLK of LSI
221
passes through a clock buffer
102
provided in LSI
221
and applied to a prebuffer
103
. Prebuffer
103
distributes this clock signal to clock lines
221
arranged in a mesh all over LSI
221
. A plurality of clock drivers
227
are prepared on, for example, cross points of clock mesh
224
. Clock drivers
227
have their outputs short-circuited with each other. In other words, there are mesh of an input line
225
and an output line
226
of the driver as shown in FIG.
1
B. The clock from output line
226
is supplied to a sequential element
228
.
In practice, sequential element
228
is arranged and routed after mesh-like clock lines
224
are prepared in an LSI. However, it is extremely rare to distribute sequential elements
228
uniformly within LSI
221
. Sequential elements
228
are often located in disproportion within a particular mesh cell. As a result, the skew increases.
An attempt has been made to reduce the skew by adjusting the driving capability of clock driver
227
and the like on the basis of the arrangement result of the sequential elements in the entire LSI
221
. It is therefore general to place clock driver
227
at a region in clock line
224
prepared therefor. This provides the advantage that the driving capability of clock driver
227
can be adjusted without having to correct the other arrangement and routing results.
In this method, the output of clock driver
227
is short-circuited. If a driver of a large delay and a driver of a small delay are present, there will be a feedback system in which a signal is output from a fast driver to a slow driver. Skew adjustment is also carried out by optimizing the driver from the eventual arrangement of the sequential elements in the LSI itself. Thus, high skew accuracy is achieved by this method.
The so-called hierarchical layout is required when the LSI complexity increases. The hierarchical layout is a method introduced to implement the LSI layout efficiently. In the hierarchical layout method, the LSI is divided into several blocks. First, layout is carried out on a block basis. Then the block having the layout completed is arranged and routed optimally, followed by the layout of the entire LSI. There is also the case where a hierarchy that has the layout already completed in another LSI is reused. Hierarchical layout is required also in this case.
The clock configuration method in the hierarchical layout of a conventional LSI
241
will be described here with reference to FIG.
2
. First, the layout of hierarchies
249
a
-
249
d
is carried out. Therefore, clocks
250
a
-
250
d
are first configured. The clock in each of hierarchies
249
a
-
249
d
can be configured in advance according to a method as shown in
FIGS. 1A and 1B
. Alternatively, a driver of a tree structure as shown in hierarchy
249
a
of
FIG. 2
can be used.
When the layout of each hierarchy has been entirely completed, the entire layout of LSI
241
is carried out using the block layout. As to the clock configuration, the clock input of each block is connected to the signal that passes through clock buffer
102
. At the clock input connection, a delay element, for example, is inserted so as to conform to the delay of the slowest clock driver, in addition to driver
251
a
that distributes the clock in order to compensate for the delay of clocks
250
a
-
250
d
to supply a clock at a low skew to all the sequential elements driven by clock signal CLK. In the example shown in
FIG. 2
, delay elements
252
a
-
252
c
are inserted supposing that clock driver
251
d
is the slowest clock driver.
In the case where the hierarchical layout is effected as described above, there are the following three types of skews.
(1) Skew of the clock configured in each block;
(2) Skew caused by clock distribution to each block from clock CLK;
(3) Skew based on a delay element to compensate for clock delay.
It is therefore extremely difficult to essentially reduce the skew since there are three causes of the skew.
According to the method configuring the clock by the entire LSI, the skew is small since there is only the skew of the configured clock. If hierarchical layout is to be effected using this method, there is the restriction in that the block can be arranged only at the position where the clock line in the block and the clock line of the LSI match due to the presence of the mesh-like clock wiring arranged all over the LSI. Therefore, layout according to this method is not easy.
Consider, for example, a case where the layout of a block is completed, and a block adjacent thereto is larger than the expected size. In order to provide a region to arrange this large block, the previous block that has the layout completed may have to be shifted from the originally planned arrangement position. However, the block can be shifted only in the unit of the mesh cell since the mesh clock lines arranged over all the LSI cannot be moved. As a result, optimum arrangement adjustment of each block at the LSI level cannot be carried out. There is a problem that the advantage of the hierarchical layout is lost.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a wiring data generation method and apparatus configuring a low skew clock corresponding to hierarchical layout.
Another object of the present invention is to provide a wiring data generation method and apparatus configuring a low skew clock that can adjust the arrangement of each block more flexibly corresponding to hierarchical layout.
A further object of the present invention is to provide a wiring data generation method and apparatus that can realize arrangement and routing corresponding to the design requirement while sufficiently making the most of previous property.
According to an aspect of the present invention, a wiring data generation method generating wiring data in designing a large-scale integrated circuit by hierarchical layout includes the steps of: generating a line in a block of a first level; carrying out layout of the block of the first level within a block of a second level higher than the first level; and generating mesh lines of the block of the second level connected to the line in the block of the first level within the block of the second level.
Since the line in the block of the first level and the mesh lines in the block of the second level are provided individually, there is no possibility of the lines at the second level being modified greatly even when the block of the first level is moved. Also, the skew occurring in the signal transmitted to the first block is small since mesh lines are formed in the block of the second level.
Preferably, the step of generating a line in the block of the first level includes the steps of generating a line surrounding the outermost perimeter of the block of the first level, and generating mesh lines of the block of the first level connected to the line surrounding the outermost perimeter wi
Do Thuan
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Smith Matthew
LandOfFree
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