Wiring board and method of producing wiring board

Details Wiring board and method of producing wiring board Wiring board and method of producing wiring board

2001-10-24

2004-02-10

Pham, Long (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

Reexamination Certificate

active

06689641

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wiring board having the resin insulating layer, a via penetrating the insulating layer, and a conductor layer formed on the resin insulating layer and via, and a method of producing the wiring board, and specifically to a wiring board in which the via and conductor layer is formed of the plating, and the via is a filled via which is filled with the plating, and a method of producing the wiring board.
2. Description of the Related Art
Conventionally, the wiring board in which a filled via penetrating the approximately plate-shaped resin insulating layer is filled with the plating and formed, and the conductor layer is formed thereon by the plating, is well known. For example, in
FIG. 9
, a wiring board
101
showing a partially enlarged sectional view of a main surface
102
side is shown. An approximately plate-shaped core board
103
is provided at the center of the wiring board
101
. The first resin insulating layer
105
is laminated on both surfaces of the core board
103
, and further, the second resin insulating layer
107
is laminated thereon. Further, on the second resin insulating layer
107
, a solder resist layer (resin insulating layer)
109
is laminated.
In them, on the core board
103
, a plurality of approximately cylindrical throughhole conductors
111
penetrating the core board, are formed at predetermined positions. Further, in the first resin insulating layer
105
, a plurality of throughholes
113
for the first via penetrating the insulating layer are formed at the predetermined positions, and in each of the throughholes
113
, the first filled via
115
is filled and formed by the plating. In the same manner, in the second resin insulating layer
107
, a plurality of through holes
117
for the second via are formed at the predetermined positions, and in each of throughholes
117
for the second via, the second filled via
119
is formed. Further, in the solder resist layer
109
, a plurality of openings
121
penetrating the resist layer, are formed at the predetermined positions in order to expose pads respectively.
The first conductor layer
123
of a predetermined pattern of the wiring or pad is formed between the core board
103
and the first resin insulating layer
105
, and connected to the throughhole
111
of the core board
103
or the first filled via
115
of the first insulating layer
105
. Further, also between the first resin insulating layer
105
and the second resin insulating layer
107
, the second conductor layer
125
of a predetermined pattern of the wiring
126
or pad
124
is formed, and is connected to the first filled via
115
of the first resin insulating layer
105
or the second filled via
119
of the second resin insulating layer
107
. Further, also between the second resin insulating layer
107
and the solder resist layer
109
, the third conductor layer
127
of a predetermined pattern of the wiring or pad
128
is formed, and is connected to the second filled via
119
of the second resin insulating layer
107
. Then, a portion of the pad
128
of the third conductor layer
127
is exposed in the opening
121
for the pad of the solder resist layer
109
, to mount the electronic parts onto the wiring board
101
.
In such the wiring boards, the first filled via
115
of the inside or the surface of the first resin insulating layer
105
and the second conductor layer
125
are formed as follows. That is, initially, by the publicly known method, the throughhole conductor
111
is formed in the core board
103
, and the first conductor layer
123
is formed on the core board
103
, and further, the board
131
formed thereon the first resin insulating layer
105
having the throughhole
113
for the first via, is prepared (refer to FIG.
10
).
Next, the electroless plating is conducted on the board
131
, and the electroless plating layer shown by a bold line in the drawing is formed on the surface of the first resin insulating layer
105
and in the throughhole
113
for the first via. Then, the plating resist layer
133
of a predetermined pattern is formed on the electroless plating layer (refer to FIG.
10
). After that, by using the plating liquid having the character in which, when the plating is conducted on a portion including the hole, the plating is more grown in the hole than the outside of the hole (hereinafter, in the present specification, the plating liquid having such the characteristic is also called the plating liquid for the filled via), the electrolytic plating is conducted on the board
131
. Then, as shown in
FIG. 10
, the plating is filled in the throughhole
113
for the first via and the first filled via
115
is formed, and the electrolytic plating layer is formed on the first filled via
115
and the electroless plating layer of the first resin insulating layer
105
.
In this connection, in the plating liquid for the filled via, in order to promote the plating growth in the hole and to inhibit the plating growth outside the hole, a leveling agent (plating inhibitor) such as N series high polymer is normally included. After, the electrolytic plating, the plating resist layer
133
is removed, and when the electroless plating layer covered by the plating resist layer
133
is removed by the etching, the second conductor layer
125
of the predetermined pattern is formed. In this manner, the first filled via
115
and the second conductor layer
125
are formed on the first resin insulating layer
105
.
After that, on the first resin insulating layer
105
and the second conductor layer
125
, the second resin insulating layer
107
is laminated, and in the same manner as described above, the second filled via
119
and the third conductor layer
127
are newly formed. Then, on the second resin insulating layer
107
and the third conductor layer
127
, when the solder resist layer
109
having the opening
121
for the pad is formed, the wiring board
101
shown in
FIG. 9
is produced.
However, when, by using the plating liquid for the filled via, the first filled via
115
and the second conductor layer
125
are formed, because the condition of the second conductor layer
125
is different depending on the position in the board
131
, the disadvantage occurs. This is considered that it is influenced from the reason that, at the time of the electrolytic plating, the current density is biased in the board
131
.
Relating to this disadvantage, when the description is specifically conducted on the board
131
shown in
FIG. 10
, in a portion in which the arrangement of the formed wiring
126
or pad
124
is coarse, that is, in a portion in which the pattern of the plating resist layer
133
is coarse, (a left side portion in the drawing), the current density becomes high at the time of the electrolytic planing, and the leveling agent in the plating liquid is easily attracted in this portion. When the vicinity of the first filled via
115
L existing in the left side portion in
FIG. 10 and a
pad
124
L of the second conductor layer
125
is observed, as a partially enlarged sectional view is shown in
FIG. 11
, the growth of the plating particle is inhibited in the pad
124
L, as the result, the thickness of the plating layer (the thickness of the pad
124
L, that is, the second conductor layer
125
) becomes also comparatively thin. Further, as the result that the growth of the plating particle is inhibited, there is a case where an area in which the plating particle with extremely small particle diameter partly exists, is generated. In contrast to this, in a portion in which the arrangement of the wiring
126
or the pad
126
is dense, that is, in a portion in which the pattern of the plating resist layer
133
is dense, (a right side portion in the drawing), the current density at the time of the electrolytic plating is lowered, and the leveling agent in the plating solution is hardly attracted. Therefore, when the vicinity of the wiring
126
R of the second conductor layer
125
existing in the

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