Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-12-12
2006-12-12
Ray, Gopal C. (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S124000, C710S313000, C370S310000
Reexamination Certificate
active
07149839
ABSTRACT:
In wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are first attempted before asynchronous transfers, as long as the periodic transfers are successful. When failures are occurring, the hardware includes a mechanism having a software-configurable threshold specifying the number of errors a given endpoint can tolerate before it is paused in the schedule. By pausing transfer attempts that are likely to again fail, endpoints with successful transfers are favored over those experiencing errors. When the number of active transfers pending exceeds a software-configurable notification threshold for isochronous endpoints, the hardware notifies the software of this state, corresponding to a low-buffer condition at the receiver. The software may then reconfigure thresholds and deactivate other transfers to force data transfers into the buffer.
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Aull Randall E.
Bhesania Firdosh
Slick Glen T.
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