Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Configuration or pattern of bonds
Reexamination Certificate
2000-11-14
2003-03-25
Potter, Roy K. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Configuration or pattern of bonds
C257S784000, C257S659000
Reexamination Certificate
active
06538336
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor device assemblies, and in particular, to integrated-circuit packages.
BACKGROUND
Semiconductor dies are typically enclosed within a protective package that includes a variety of pin-out or mounting and interconnection schemes. More sophisticated integrated-circuit packages have been developed for very large scale integration (“VLSI”) semiconductor dies. Such integrated circuit packages can accommodate the increased number of external connections required for packaging ever more complex integrated circuits.
FIG. 1A
(Prior Art) depicts a portion of a semiconductor device assembly
100
. Assembly
100
includes a wiring board
105
upon which is mounted a semiconductor die
110
. Wiring board
105
includes an insulating substrate
115
upon which is formed a number of patterned conductive features, including a number of bond sites
120
, bond traces
125
, and a power trace
130
(though not shown, power trace
130
typically surrounds die
110
). Bond sites
120
, often referred to as bond “fingers,” are areas of metalization having dimensions specified by the selected bonding process.
Semiconductor die
110
includes a number of gold-plated bond pads
135
that provide access to electrical circuits (not shown) within semiconductor die
110
. Gold bond wires
140
extending between bond pads
135
and either power trace
130
or bond sites
120
allow semiconductor die
110
to receive power from and communicate signals to and from wiring board
105
. Bond sites
120
and power trace
130
are further connected by vias and conductive leads (not shown) to some external circuitry with which the circuitry within die
110
is to communicate. Wire bonds
142
, or just “bonds,” connect bond sites
120
and bond pads
135
to bond wires
140
.
Power trace
130
connects a number of bond pads
135
to DC power signals, such as VDD or ground potential. Additional power rings may also be provided, but are omitted here for simplicity. Bond sites
120
may also connect to DC power signals, but are more often used to transmit digital logic signals between semiconductor die
110
and wiring board
105
. In
FIG. 1A
, bond wires conveying power signals are designated using dashed lines, whereas bond wires conveying signals having alternating voltage levels (e.g., clock and data lines) are designated using solid lines.
The term “semiconductor device assembly” refers to a semiconductor die, one or more wiring boards, and the associated structure with which the semiconductor die is connected, including connections to a socket or system printed circuit board, and internal connections such as bond wiring. For a more detailed description of a semiconductor device assembly similar to the one described in
FIGS. 1A and 1B
, see U.S. Pat. No. 5,741,726 to I. Barber, which is incorporated herein by reference.
As integrated circuit fabrication technology improves, manufacturers are able to integrate additional and faster functions onto a single semiconductor device. The increased number of functions mandates additional and more closely spaced signal paths between the semiconductor die and the corresponding wiring board, while the increased speed renders adjacent signals more sensitive to errors induced by higher mutual coupling between adjacent signal lines. Power planes (e.g., a ground plane) extending beneath bond pads, bond sites, and bond traces reduce mutual inductance between surface features. Returning to
FIG. 1A
, for example, wire board
105
includes a power plane
145
that extends beneath bond sites
120
and bond traces
125
to reduce mutual coupling. Unfortunately, such planes do little to shield bond wires, which extend well above the wiring board. Consequently, mutual coupling, also known as “cross-talk,” is particularly problematic between bond wires.
FIG. 1B
(Prior Art) is a profile view of semiconductor device assembly
100
of FIG.
1
A. As is typical, bond pads
135
are arranged in rows parallel with an edge of die
110
, an exterior row
150
(exterior to the center of die
110
) and an interior row
155
in the depicted embodiment. The bond wires
140
extending from interior row
155
to respective ones of bond sites
120
share a common wire-loop profile
160
. In contrast, the bond wires
140
from exterior row
150
alternatively extend to power trace
130
and bond sites
120
, and consequently present two distinct wire-loop profiles
165
and
170
, respectively. Profiles
165
and
170
define a current-loop area
175
; unfortunately, current-loop area
175
results in excessive magnetic flux linkage and mutual inductive coupling between neighboring signal wires. High-frequency electrical performance suffers as a result, a significant disadvantage in an industry where speed-performance is paramount. There is therefore a need for a semiconductor device assembly that offers improved speed performance.
SUMMARY
The present invention is directed to a semiconductor device assembly that enables integrated circuits to communicate with external circuitry at higher speeds. In an embodiment that includes an integrated circuit die with interior and exterior bond-pad rows arranged along an edge of the die, the die is mounted on a wiring board that includes exterior and interior wire-bond rows and a novel arrangement of bond traces conveying signals to and from, the bond sites. Bond wires connect each bond pad in the external bond-pad row to a corresponding bond site in the internal wire-bond row, and other bond wires connect each bond pad in the internal bond-pad row to a corresponding bond site in the external wire-bond row. This arrangement minimizes the current-loop areas between bond wires adapted to carry high-speed signals, and therefore minimizes the cross coupling between adjacent signal lines.
In one embodiment, the bond pads and bond sites are arranged so the bond wires that extend between them collectively form a portion of a high-speed data bus for conveying a plurality of fast-switching signals. This embodiment minimizes cross-talk between neighboring signal lines by extending a bond wire conveying a DC (e.g., power-supply) voltage between each pair of bond wires conveying fast-switching signals. Preferably, no high-speed signals in the same bus are present on adjacent bond wires. In addition to separating the bond wires extending from each row, another embodiment provides further shielding by arranging DC or slow-switching bond wires above or below high-speed bond wires in an adjacent row. In this configuration, bond wires conveying high-speed signals are shielded by adjacent bond wires in the same row and by adjacent bond wires above.and/or below in other rows. This arrangement advantageously facilitates high-speed communication between integrated circuits and external circuits and further allows for closer spacing of bond wires.
This summary does not limit the invention, which is instead defined by the appended claims.
REFERENCES:
patent: 5616952 (1997-04-01), Nakano et al.
patent: 5734559 (1998-03-01), Banerjee et al.
patent: 5741726 (1998-04-01), Barber
patent: 5801450 (1998-09-01), Barrow
patent: 5818114 (1998-10-01), Pendse et al.
patent: 6008532 (1999-12-01), Carichner
patent: 6043559 (2000-03-01), Banerjee et al.
patent: 6064113 (2000-05-01), Kirkman
Jain Nirmal
Secker David A.
Behiel Arthur J.
Potter Roy K.
Rambus Inc.
LandOfFree
Wirebond assembly for high-speed integrated circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Wirebond assembly for high-speed integrated circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wirebond assembly for high-speed integrated circuits will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3033496