Wire width planning and performance optimization for VLSI...

Details Wire width planning and performance optimization for VLSI... Wire width planning and performance optimization for VLSI...

2000-02-22

2002-06-18

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06408427

ABSTRACT:

BACKGROUND OF TEE INVENTION
1. Field of the Invention
The present invention relates generally to electronic design automation (EDA) systems, and in particular, to a method, apparatus, and article of manufacture for wire width planing and performance optimization for very large scale integration (VLSI) interconnects.
2. Description of the Related Art
(Note: This application references a number of different publications as indicated throughout the specification by reference numbers enclosed in brackets, e.g., [x]. A list of these different publications ordered according to these reference numbers can be found below in Section 7 of the “Detailed Description of the Preferred Embodiment”. Each of these publications is incorporated by reference herein.)
For deep submicron (DSM) designs of VLSI circuits, wiring delay has exceeded transistor delays, and thus has become the dominant factor in determining overall circuit performance [
12
,
3
]. To achieve minima wire delay, a number of techniques have been introduced for optical wire sizing, by using continuous wire shaping [
9
,
1
,
2
] or discrete wire tapering with many discrete wire widths [
5
,
4
,
3
] in an interconnect structure to optimize the interconnect performance. These techniques, however, will considerably complicate the layout design, especially the detailed routing, due to their use of possibly large number of different wire widths. Moreover, it is difficult to plan and allocate proper routing resources at design planning stages for these wire sizing optimizations, which is necessary to achieve the overall design and timing convergence.
Thus, there is a need in the art for simplified wire sizing schemes. Moreover, there is a need in the art for wire width planning and optimization for VLSI interconnect performance optimization.
SUMMARY OF THE INVENTION
To address the requirements described above, the present invention discloses a method, apparatus, and article of manufacture for wire width planning and optimization for VLSI interconnect performance optimization. Two simplified wire sizing schemes are described for an interconnect structure, namely the single-width sizing method (1-WS) and the two-width sizing method (2-WS). These simplified wire sing schemes have near optimal performance as compared to complex wire sizing methods with many or even an infinite number of wire widths. A wire width planning method is then described to determine a small set of globally optimal wire widths for VLSI interconnects in a range of lengths. It is concluded that near optimal interconnect performance can be achieved by using such a pre-designed, very limited number of wire widths (usually two-width design is adequate). The layout for the VLSI interconnects is then generated and optimized using the limited number of planned wire widths. As a result, the resulting layout is greatly simplified.


REFERENCES:
patent: 5793643 (1998-08-01), Cai
patent: 5841333 (1998-11-01), Fishburn et al.
C.P. Chen et al., Optimal wire-sizing formula under the Elmore delay model, in Proc. Design Automation Conf., pp. 487-490, 1996.
C.P. Chen et al., Optimal wire sizing function with fringing capacitance consideration, in Proc. Design Automation Conf., pp. 604-607, 1997.
J. Cong et al., Interconnect design for deep submicron ICs, in Proc. Int. Conf. on Computer Aided Design, pp. 478-485, 1997.
J. Cong et al., Optimal wiresizing under the distributed Elmore delay model, in Proc. Conf. on Computer Aided Design, pp. 634-639, 1993.
J. Cong et al., Interconnect estimation and planning for deep submicron designs, in Proc. Design Automation Conf., pp. 507-510, 1999.
J. Cong et al., Global interconnect sizing and spacing with consideration of coupling capacitance, in Proc. Int. Conf. on Computer Aided Design, pp. 623-633, 1997.
Semiconductor Industry Association, National Technology Roadmap for Semiconductors, 1997, pp. 1-196, no other name.
J. Davis et al., Is Interconnect the weak link?, in IEEE Circuits and Devices Magazine, vol. 14, No. 2, pp. 30-36, 1998.
R. Otten et al., Planning for performance, in Proc. Design Automation Conf., pp. 122-127, Jun. 1998.
P. Fisher et al., The test of time clock-cycle estimation and test challenges for future microprocessors, IEEE Circuits and Devices Magazines, vol. 14, pp. 37-44, Mar. 1998.
J. Davis et al., A stochastic wire-length distribution for gigascale integration (GSI) i. derivation and validation, IEEE Transactions on Electron Devices, vol. 45, No. 3, pp. 580-589, 1998.

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