Wire tapering under reliability constraints

Details Wire tapering under reliability constraints Wire tapering under reliability constraints

1999-04-26

2001-10-23

Nelms, David (Department: 2763)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

06308303

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuit interconnects and in particular the present invention relates to determining interconnect widths.
BACKGROUND OF THE INVENTION
Integrated circuits are fabricated with a plurality of circuits distributed across a chip, or die. The distributed circuits are electrically connected using conductive interconnect networks. For simplicity, these conductive interconnects are referred to herein as wires. It will be understood, however, that the electrical interconnects are conductive or semiconductor material fabricated as traces having a length, width and thickness. The physical dimensions, layout and material composition dictate the electrical characteristics of the interconnect. That is, for a given material the physical dimensions dictate the resistance of the conductive trace, its electrical current capacity and its capacitance. Integrated circuit designers are faced with the challenge of minimizing signal delay experienced as a voltage signal propagates along the interconnect network. Computer aided tools and algorithms have been developed to assist in determining interconnect physical dimensions to improve time critical networks. For example, see J. Cong, K. S. Leung, Optimal Wiresizing Under Elmore Delay Model, IEEE Transactions on Computer-Aided Design of Circuits and Systems, March 1995, pp. 321-336, for a description of an algorithm which can be used to determine optimal wire widths using tapering techniques to improve timing characteristics.
Wire tapering is a design technique in which wires which are close to a driver circuit are made wider than wires which are close to receiver circuits. This reduces the capacitance of the signal path and increases the spacing between adjacent wires, effectively reducing interconnect delay, power consumption and cross talk in integrated circuits.
Electromigration and self-heating phenomena place constraints on the minimum allowed width of a wire, depending on the current flow through the wire. In academic and commercial tapering solutions, these phenomena are not accounted for. The solutions produced using these techniques result in wires which must be widened by manually editing the resultant design. If this manual editing is not performed, an integrated circuit may be fabricated which has reliability problems. That is, a fuse-type conductor will be created if a wire width is selected which is not sufficient to carry a required current. Over the life of the integrated circuit, therefore, the conductor may fail.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a tool which allows circuit designers to determine optimal interconnect network configurations without compromising a reliability of the integrated circuit.
SUMMARY OF THE INVENTION
In one embodiment, a method is provided for determining interconnect wire widths in a wiring network. The method comprises calculating a minimum width of directed interconnects having a defined electrical current path. The minimum width is calculated based upon a determined downstream capacitance and an electrical current value. A first interconnect width is calculated for each undirected interconnect in the network having an ambiguous electrical current path direction. The first interconnect width is calculated by determining a first downstream capacitance in a first interconnect direction, determining a second downstream capacitance in a second interconnect direction which is opposite the first interconnect direction, and calculating a first interconnect width based upon the first and second downstream capacitances. After the first interconnect width is calculated for each undirected interconnect, additional widths for the undirected interconnects are calculated until a convergence is reached such that the additional widths remain constant.
In another embodiment, a method is provided for selecting interconnect wire widths in a wiring network. The method comprises determining a first width of an interconnect wire based upon electrical power requirements of the interconnect wire, and determining a second width of the interconnect wire based upon signal propagation timing requirements. A final width of the interconnect wire is selected such that the final width is either equal to the first width if the first width is greater than the second width, or equal to the second width if the second width is greater than the first width.


REFERENCES:
patent: 5410490 (1995-04-01), Yastrow
patent: 5737580 (1998-04-01), Hathaway et al.
patent: 5841333 (1998-11-01), Fishburn et al.
patent: 6028989 (2000-02-01), Dansky et al.
patent: 6117182 (2000-09-01), Alpert et al.
Cong, J.J., et al., “Optimal Wiresizing Under Elmore Delay Model”,IEEE Transactions on Computer-Aided Design of Circuits and Systems, 14, pp. 321-336, (Mar. 1995).

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