Wire forming method for semiconductor device

Details Wire forming method for semiconductor device Wire forming method for semiconductor device

1995-11-20

1997-02-18

Niebling, John

Fishing, trapping, and vermin destroying

1566441, H01L 2144

Patent

active

056041560

ABSTRACT:
A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.

REFERENCES:
patent: 4832789 (1989-05-01), Cochran et al.
patent: 5063176 (1991-11-01), Lee et al.
patent: 5354712 (1994-10-01), Ho et al.
patent: 5451551 (1995-09-01), Krishnan et al.
Anonymous, "Edge sloping via holes . . . " (Jul. 1988) Research Disclosure 291,013.

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