Wire delay distributed model

Details Wire delay distributed model Wire delay distributed model

2005-04-12

2005-04-12

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06880141

ABSTRACT:
An improved method of using the Elmore Model to estimate the delay which is associated with the a clock buffer output. The improved method provides that the clock buffer output resistor is taken into account when the Elmore Model is used to calculate the delay. Also provided is a method of using the Elmore Model to estimate wire delay, where the method includes steps of calculating an approximate delay based on a distributed RC model, and using a capacitance value corresponding to the approximate delay in the Elmore Model to estimate the wire delay.

REFERENCES:
patent: 5469366 (1995-11-01), Yang et al.
patent: 6044209 (2000-03-01), Alpert et al.
patent: 6347393 (2002-02-01), Alpert et al.
patent: 6606587 (2003-08-01), Nassif et al.
Kashyap et al., “An “Effective” Capacitance Based Delay Metric for RC Interconnect”, IEEE, 2000.*
Lukas Van Ginneken, “Buffer Placement in Distributed RC-Tree Networks for Minimal Elmore Delay”, IBM, Thomas J. Watson Research Center, IEEE, 1990, pp. 865-868.*
IBM Technical Disclosure Bulletin, “Buffer Placement in Distributed RC Tree Networks for Minimal Elmore Delay”, vol. 33, No. 8 Jan. 1991, pp. 338-341.

Affiliated with

Also associated with

Rating

Wire delay distributed model does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Wire delay distributed model, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Wire delay distributed model will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3380609