Wire bonding structure for semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Wire contact – lead – or bond

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Details

257700, 257705, 257734, 257697, H01L 23053, H01L 2306, H01L 2348

Patent

active

056274084

ABSTRACT:
A semiconductor substrate is positioned in a cavity formed at the center of the major surface of a mounting portion. A plurality of inner leads comprising signal leads and power supply leads are arranged along the peripheral area of the major surface of the mounting portion, with their ends opposed to the semiconductor substrate. The inner leads are connected to the semiconductor substrate by way of bonding wires. All of the bonding wires connecting the signal leads to the semiconductor substrate have substantially the same length. The inner leads are formed on the surfaces of the ceramic layers that are partially laid one on the other to form a multilayer structure. The ceramic layer supports the signal leads and has a polygonal opening or cavity, the number of the corners of which is greater than that of the mounting portion. The ceramic layer may have a stepped profile in which a surface portion of the ceramic layer which is close to the corners of the mounting portion is high and a surface portion of the ceramic layer which is close to the middle portion of the edges of the mounting portion is low. With the above structure, variation in length of the bonding wires connecting the signal leads to the corresponding bonding pads on the semiconductor substrate can be reduced.

REFERENCES:
patent: 4924297 (1990-05-01), Denda
patent: 5008734 (1991-04-01), Dutta et al.
patent: 5245214 (1993-09-01), Simpson

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