Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2000-12-20
2003-11-04
Karlsen, Ernest (Department: 2829)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S686000, C257S777000, C257S784000
Reexamination Certificate
active
06642610
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a wire bonding method and a semiconductor package manufactured using the method, and, more particularly, the present invention relates to a wire bonding method and semiconductor package including a plurality of electrically interconnected semiconductor chips.
2. Description of the Related Art
Conventionally, a semiconductor package may include a plurality of semiconductor chips that are stacked or arranged side by side on a printed circuit board, a lead frame or a circuit film. (The descriptions below will be given mainly with reference to a printed circuit board.) Such semiconductor packages are known as stack-type semiconductor packages or multi-chip module (MCM) packages, respectively.
Often in such packages, one or more of the semiconductor chips are electrically connected to metal circuit patterns of the printed circuit board through conductive wires, which are sometimes called bond wires. The semiconductor chips are also electrically connected to one another through conductive wires bonded between their respective input and output pads.
A stack-type semiconductor package
100
′ is illustrated in
FIG. 1
a,
and a state of the stack type semiconductor package before encapsulation is illustrated in
FIG. 1
b.
As shown in
FIGS. 1
a
and
1
b,
a first semiconductor chip
2
is provided. A plurality of rows (for example, two staggered rows) of first input and output pads
2
a
are formed on an upper surface of the first semiconductor chip
2
. A second semiconductor chip
4
is stacked on and affixed to the upper surface of the first semiconductor chip
2
by an adhesive means
6
. Semiconductor chip
4
is located within input and output pads
2
a
of semiconductor chip
2
. One row of second input and output pads
4
a
is formed on an upper surface of the second semiconductor chip
4
.
A printed circuit board
20
is affixed to a lower surface of the first semiconductor chip
2
by another adhesive means
6
.
As well known in the art, the printed circuit board
20
includes a resin layer
22
. Electrically conductive circuit patterns are formed on the upper and lower surfaces of the resin layer
22
. In particular, first circuit patterns
24
, which include bond fingers
24
a,
are formed on the upper surface of the resin layer
22
outside the perimeter of first semiconductor chip
2
. Second circuit patterns
24
, which include ball lands
24
b,
are formed on the lower surface of the resin layer
22
. The first and second circuit patterns
24
are electrically connected with each other through via-holes
25
through resin layer
22
. On the upper surface of the resin layer
22
, the first circuit patterns
24
, excluding the bond fingers
24
a,
are coated with cover coats
26
or the like. Likewise, on the lower surface of the resin layer
22
, the second circuit patterns
24
, excluding the ball lands
24
b,
are coated with cover coat
26
or the like.
Some of the first input and output pads
2
a
of the first semiconductor chip
2
are electrically connected to second input and output pads
4
a
of the second semiconductor chip
4
through first conductive wires
8
a
that extend between them. Other first input and output pads
2
a
of the first semiconductor chip
2
are electrically connected to the bond fingers
24
a
of the printed circuit board
20
through second conductive wires
8
b.
Particular wires
8
a,
8
b
may carry a ground voltage, power supply voltage, or data/instruction signals.
A hardened encapsulating section
30
of a predetermined shape covers the first semiconductor chip
2
, the second semiconductor chip
4
, the first and second conductive wires
8
a
and
8
b,
and the inner portion of the upper surface of circuit board
20
, thereby protecting those components from the external environment.
Conductive balls
40
are fused to the ball lands
24
b
on the lower surface of the printed circuit board
20
, and function as input and output terminals for communication with semiconductor chips
2
,
4
.
Hereinafter, a method for electrically connecting the first and second semiconductor chips
2
and
4
with each other through the conductive wires
8
a
and for electrically connecting first semiconductor chip
2
and the bond fingers
24
a
of the printed circuit board
20
through conductive wires
8
b
will be described with reference to
FIGS. 2
a
through
2
d.
First, conductive balls
8
d
each having a predetermined size are formed with a wire bonder on some of the first input and output pads
2
a
of first semiconductor chip.
2
. After the balls
8
d
are formed, the conductive wires drawn from balls
8
d
are cut off (see
FIG. 2
a
). The drawing reference numeral
50
represents a capillary portion of a wire bonder for implementing a wire boding operation.
Then, to electrically connect the two semiconductor chips
2
and
4
, one end of each of a plurality of conductive wires
8
a
are bonded to selected ones of the second input and output pads
4
a
of the second semiconductor chip
4
, and the opposite end of those conductive wires
8
a
are each connected to one of the conductive balls
8
d
that were previously formed on some of the first input and output pads
2
a
of the first semiconductor chip
2
(see
FIGS. 2
b
and
2
c
). To accomplish this wire bond between semiconductor chips
2
and
4
, balls are formed by capillary
50
using the conductive wire material, and the balls are fused to the selected second input and output pads
4
a
of the second semiconductor chip
4
. Capillary
50
then forcibly squeezes and fuses the opposite portion of each conductive wire against a ball
8
d.
Next, capillary
50
cuts the conductive wire.
Subsequently, wire bonds
8
b
are connected between other first input and output pads
2
a
of the first semiconductor chip
2
and bond fingers
24
a
of printed circuit board
20
.
However, this conventional wire bonding method, and the resulting semiconductor packages, suffer from defects due to the fact that conductive balls
8
d
are formed in advance on some of the input and output pads of the first semiconductor chip
2
, afterwhich an end of a wire
8
a
is bonded to each of the balls
8
d.
This can lead to an inferior wire bond connection, and reduced bonding yield.
Moreover, since the wire bonding operation is implemented in a manner that brings capillary
50
into contact with the conductive balls
8
d,
the lifetime of capillary
50
can be shortened, and the tip of capillary
50
can be seriously contaminated with the material of balls
8
d.
Furthermore, because a separate process for forming the conductive balls
8
d
is required, wire bonding time is lengthened and the manufacturing cost of the entire semiconductor package is increased.
On the other hand, if the first and second semiconductor chips were directly wire bonded with each other without conductive balls
8
d,
the input and output pads of the first semiconductor chip
2
can be broken by vibration energy of capillary
50
, or first semiconductor chip
2
itself can be cracked by capillary
50
. In view of this grave possible outcome, the wire bonding method using conductive balls
8
d
has been adopted.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a wire bonding method for a semiconductor package containing a plurality of semiconductor chips. The semiconductor chips may be stacked one on top the other or arranged side by side on the same horizontal plane. The plural semiconductor chips are electrically interconnected using the disclosed methods without suffering from the problems associated with the conventional wire bonding methods described above.
Another object of the present invention is to provide a wire bonding method which can lengthen the lifetime of a capillary of a wire bonder and reduce manufacturing costs.
Another object of the present invention is to provide a reliable semiconductor package that includes a plurality of electrically interconnected semiconductor chips (either stacked
Han Byung Joon
Kim Jae Dong
Park Young Kuk
Amkor Technology Inc.
Bever Hoffman & Harms LLP
Geyer Scott B.
Parsons James E.
LandOfFree
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