Wire-bonded semiconductor device with improved wire...

Details Wire-bonded semiconductor device with improved wire... Wire-bonded semiconductor device with improved wire...

2000-09-30

2002-08-27

Williams, Alexander O. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Wire contact, lead, or bond

C257S776000, C257S786000, C257S692000, C257S693000, C257S666000, C228S180500

Reexamination Certificate

active

06441501

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a wire-bonded semiconductor device with an improved wire-arrangement scheme that can help minimize abnormal wire sweep due to the bonding wires being shoved by the flow of injected resin during encapsulation process.
2. Description of Related Art
A semiconductor chip is typically enclosed in a protective package before it is mounted on a circuit board. Various types of semiconductor packaging technologies are presently utilized in the semiconductor industry. The wire bond technology is widely utilized to electrically couple the semiconductor chip by means of a plurality of bonding wires to a substrate on which the semiconductor chip is mounted.
As semiconductor devices are made smaller and smaller, the wire-bonding process is becoming more critical since the bonding wires are also proportionally reduced to very small sizes and pitches. During encapsulation process, however, such small and densified bonding wires would be easily shoved by the flow of the injected encapsulation material, such as resin, and would consequently be displaced sideways toward adjacent wires. This sideward displacement in the bonding wires is customarily referred to as abnormal wire sweep. The problem of abnormal wire sweep is illustratively depicted in the following with reference to
FIG. 1
,
FIG. 2
, and
FIGS. 3A-3B
.
FIG. 1
is a schematic diagram showing the encapsulation of a wire-bonded semiconductor device
10
. As shown, the wire-bonded semiconductor device
10
is substantially qaudrilaterally-shaped having four corners
10
a,
10
b,
10
c,
10
d.
During the encapsulation process, the wire-bonded semiconductor device
10
is mounted inside an encapsulation mold
40
, with the corner
10
a
thereof being aligned to the resin inlet gate
41
from which an encapsulation material, typically resin, is injected in liquid state (as indicated by the arrows in
FIG. 1
) onto the wire-bonded semiconductor device
10
.
In the case of
FIG. 1
, the problem of abnormal wire sweep would likely occur in the nearby corners
10
b,
10
d
located in immediate adjacency to the resin-receiving corner
10
a.
The cause of this problem is depicted below.
FIG. 2
is a schematic diagram showing the wire arrangement in the corner
10
b
of the wire-bonded semiconductor device
10
shown in FIG.
1
. As shown, the wire-bonded semiconductor device
10
includes a semiconductor chip
11
and a substrate
20
on which the semiconductor chip
11
is mounted. The semiconductor chip
11
is formed with a plurality of bond pads
12
(hereinafter referred to as “chip-side bond pads”) on the periphery thereof; and correspondingly, the substrate
20
is formed with a plurality of bond pads
21
(hereinafter referred to as “substrate-side bond pads”) on the top surface thereof. A set of bonding wires
30
are interconnected between the chip-side bond pads
12
and the substrate-side bond pads
21
for electrically coupling the semiconductor chip
11
to the substrate
20
.
The bonding wire set
30
includes two subsets: a first wire subset
31
and a second wire subset
32
. The first wire subset
31
includes a number of bonding wires (only three are shown in
FIG. 2
, respectively designated by the reference numerals
31
a,
31
b,
31
c
), which are located along one side of the wire-bonded semiconductor device
10
adjoining the corner
10
b.
The second wire subset
32
includes a number of bonding wires, for example a pair of bonding wires
32
a,
32
b,
which are located in the corner
10
b
of the wire-bonded semiconductor device
10
and in immediate adjacency to the first wire subset
31
.
The bonding wires
31
a,
31
b,
31
c
in the first wire subset
31
are typically functional wires, such as signal and power wires; whereas the bonding wires
32
a,
32
b
in the second wire subset
32
are typically non-functional bonding wires, such as grounding wires (G/W).
Referring further to
FIGS. 3A-3B
, the first wire subset
31
and the second wire subset
32
are wired in such a manner as to extend from the chip-side bond pads
12
along a looped trajectory down to the substrate-side bond pads
21
. To allow high wire pitch, the bonding wires
31
a,
31
b,
31
c
in the first wire subset
31
are all set to a large loop height of H
1
as illustrated in
FIG. 3A
; while the bonding wires
32
a,
32
b
in the second wire subset
32
are all set to a small loop height of H
2
, where H
2
<H
1
, as illustrated in
FIG. 3B
(in this specification, the term “loop height” refers to the vertical distance from the top surface of the semiconductor chip
11
to the highest point of the bonding wire).
Referring back to
FIG. 2
, since the bonding wires
31
a,
31
b,
31
c
in the first wire subset
31
are greater in loop height than the bonding wires
32
a,
32
b
in the second wire subset
32
, the foremost bonding wire
31
a
in the first wire subset
31
located in immediate adjacency to the first wire subset
31
would face directly against the flow of injected resin (not shown) and thus would likely be shoved to displace sideways toward the neighboring bonding wire
31
b.
This sideward wire displacement is customarily referred to as abnormal wire sweep, which may easily cause the foremost bonding wire
31
a
in the first wire subset
31
to be short-circuited to the neighboring bonding wire
31
b.
A variety of patented semiconductor fabrication technologies have been proposed as a solution to the problem of abnormal wire sweep. A few of these patented technologies are listed in the following:
U.S. Pat. No. 6,031,281 entitled “SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING DUMMY BONDING WIRES”;
U.S. Pat. No. 5,780,772 entitled “SOLUTION TO MOLD WIRE SWEEP IN FINE PITCH DEVICES”;
U.S. Pat. No. 5,684,332 entitled “METHOD OF PACKAGING A SEMICONDUCTOR DEVICE WITH MINIMUM BONDING PAD PITCH AND PACKAGING DEVICE THEREFROM”.
These patented technologies solve the problem of abnormal wire sweep by providing dummy wires among the bonding wires. One drawback to the provision of dummy wires, however, is that it would make the wire-bonding process significantly more complex to implement.
SUMMARY OF THE INVENTION
It is therefore an objective of this invention to provide a wire-bonded semiconductor device with an improved wire-arrangement scheme that can help minimize abnormal wire sweep without using dummy wires.
In accordance with the foregoing and other objectives, the invention proposes a wire-bonded semiconductor device with an improved wire-arrangement scheme.
In one preferred embodiment, the wire-bonded semiconductor device of the invention comprises: (a) a substrate having a plurality of bond pads; (b) a semiconductor chip mounted on the substrate, the semiconductor chip having a plurality of bond pads; and (c) a set of bonding wires interconnected between the chip-side bond pads and the substrate-side bond pads for electrically coupling the semiconductor chip to the substrate; the bonding wire set including: (c1) a first wire subset arranged along one side of the wire-bonded semiconductor device and erected to a first loop height; and (c2) a second wire subset arranged in adjacency to the first wire subset in a corner of the wire-bonded semiconductor device; the second wire subset including a number of bonding wires, with the one located in immediate adjacency to the first wire subset being erected to the first loop height, and every other one being erected to a second loop height smaller than the first loop height.
In another preferred embodiment, the wire-bonded semiconductor device of the invention comprises: (a) a substrate having a plurality of bond pads including at least one double-wire bond pad; (b) a semiconductor chip mounted on the substrate, the semiconductor chip having a plurality of bond pads; and (c) a set of bonding wires interconnected between the chip-side bond pads and the substrate-side bond pads for electrically coupling the semiconductor chip to the substrate; the bo

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