Wideband communication using delay line clock multiplier

Details Wideband communication using delay line clock multiplier Wideband communication using delay line clock multiplier

2007-06-19

2007-06-19

Tran, Khanh (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

Reexamination Certificate

active

09837760

ABSTRACT:
A delay line clock multiplier is disclosed for use in a communication system, in which a delay line is used as a clock multiplier for generating a higher speed clock that may be used, for example, for data sampling. The speed and timing characteristics of the clock delay line are adjusted by controlling the supply voltage to the delay line. because proper synchronization may be achieved at the higher frequencies using an oversampling synchronization approach which in turn is made possible by the delay line clock multiplier which allows for the oversampling of a signal at sub-interval increments.

REFERENCES:
patent: 5796313 (1998-08-01), Eitan
patent: 5926053 (1999-07-01), McDermott et al.
patent: 6275547 (2001-08-01), Saeki
patent: 6404833 (2002-06-01), Takebe
patent: 6650661 (2003-11-01), Buchanan et al.
patent: 6674824 (2004-01-01), Chiueh et al.
patent: 6721379 (2004-04-01), Cranford et al.

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