Wide frequency range delay locked loop

Details Wide frequency range delay locked loop Wide frequency range delay locked loop

2011-08-16

2011-08-16

Odom, Curtis B (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S371000, C375S373000, C375S375000, C327S147000, C327S148000, C327S149000, C327S150000, C327S151000, C327S155000, C327S156000, C327S157000, C327S159000, C327S160000, C327S161000

Reexamination Certificate

active

08000430

ABSTRACT:
A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

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