Wide bit memory using post passivation interconnection scheme

Details Wide bit memory using post passivation interconnection scheme Wide bit memory using post passivation interconnection scheme

2001-03-07

2002-06-04

Meier, Stephen D. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S311000, C257S228000

Reexamination Certificate

active

06399975

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an integrated circuit thick metal structure. More particularly, the invention relates to a wide-bit memory output structure.
2. Description of the Related Art
In a context where a general trend is to reduce the size of integrated circuits, the emphasis consequently is also to miniaturize metallic interconnections internal to integrated circuit devices. However, this miniaturization produces negative effects, among which is a substantial reduction of the chip performance. More particularly, an extreme miniaturization of interconnections causes a serious voltage drop to power and ground buses, and also causes resistor-capacitor delay (RC delay) and noises issues to the critical signal path.
FIG. 1
shows a memory structure known in the art, wherein a chip
100
is provided conventionally with a plurality of output driver circuit cells
102
, an output delay circuit
104
, a memory clock circuit
106
, a power bus
108
and a ground bus
110
, a plurality of power lines
112
, a plurality of ground lines
114
, a plurality of signal lines
116
, a plurality of control lines
118
, and a clock line
120
therein. A first surface of the chip
100
is covered with a passivation layer
122
, at the surface of which are exposed a power bonding pad
124
, a ground bonding pad
126
and a signal bonding pad
128
. Moreover, the plurality of output driver circuit cells
102
respectively has a power node
130
, a ground node
132
, a signal node
134
and a control node
136
. The interconnection scheme of an output driver circuit cell
102
in such a structure is as follows. A power supply path is provided to the output driver circuit cell
102
through connecting to one another successively the power bonding pad
124
, the power bus
108
, the power line
112
and the power nodes
130
of output driver circuit cell
102
. In the same manner, a connection to the ground of the output driver circuit cell
102
is provided through connecting to one another successively the ground node
132
of output driver circuit cell
102
, the ground line
114
, the ground bus
110
, and the ground bonding pad
130
. A signal path to the output driver circuit cell
102
is provided through connecting the signal bonding pad
134
of output driver circuit cell
102
through the signal line
116
to the signal bonding pad
128
. The clock memory circuit
106
is connected to the output delay circuit
104
through the clock line
120
, while the output delay circuit
104
in turn is connected to the control node
136
of output driver circuit cell
102
through the control line
118
. The lines of the memory chip
100
is conventionally made of aluminum or aluminum alloy. Besides, the line width is extremely narrow, which results in noise and RC delay issues when a large current passes through therein. These issues cause serious negative effects to the operating of the memory chip, among which is an inefficient connection of all the output driver circuit cells
102
to both the power bus
108
and the ground bus
110
, because the cross-section surface of the buses is excessively small.
Conventionally, an access to a word of stored data is performed through a plurality of output driver circuit cells
102
and, in order to increase the speed, those operations are performed preferably simultaneously. However, when the word width increases, for instance when a plurality of bytes is to be loaded simultaneously, the power bus
108
and the ground bus
110
suddenly have to supply much higher current flow, which may result in ground bounce or voltage sagging noise and may create errors. Therefore, an output delay circuit
104
is conventionally used to control the driving of a plurality of output driver circuit cells
102
. In such a solution, the driving operation is typically controlled through the clock circuit
106
, and the access is performed by segment, which results in a smaller number of output driver circuit cells
102
driven each time. As a result, an excessive current flow is prevented from occurring. This solution is not satisfactory from an efficiency point of view, because the circuits hence tend to be designed with more complexity, which results in an increase of silicon estate.
SUMMARY OF THE INVENTION
The present invention provides a wide-bit memory output structure, wherein a plurality of output circuit cells can be driven each time, which results in an increase of access bandwidth of the chip.
Another advantage of the wide-bit memory output structure of the present invention is that the design of the circuit can be substantially simplified.
Still, another advantage of the wide-bit memory output structure is that the noise occurrence and the RC delay are substantially reduced, which results in a better access reliability.
Still, another advantage of the wide-bit memory output structure is that the resistivity of signal lines is reduced substantially.
Still, another advantage of the wide-bit memory output structure is that the fabrication cost can be substantially reduced.
In view of at least the above, the present invention provides a wide-bit memory output structure that comprises a memory chip coupled to a thick metal structure. The memory chip comprises a plurality of output driver circuit cells, a plurality of first power lines, a plurality of first ground lines, a plurality of first signal lines, wherein each of the output driver circuit cells comprises respectively a power node, a ground node, and a signal node. The interconnection scheme of each of the output driver circuit cell is as follows. A first power line and a power node of the output driver circuit cell are connected to each other, a first ground line and a ground node of the output driver circuit cell are connected to each other, and a signal line and a signal node of the output driver circuit cell are connected to each other. An extremity of respectively first power line, first ground line, and first signal line is exposed at the surface of the memory chip. The thick metal structure comprises at least a composite dielectric material and a patterned trace structure. The patterned trace structure interlaces inside the composite dielectric material, and comprises at least a wide power bus, at least a wide ground bus, a plurality of second power lines, a plurality of second ground lines, and a plurality of second signal lines. The interconnection between the thick metal structure and an output driver circuit cell is as follows. A second power line and a first power line of the memory chip are connected to each other, a second ground line and a first ground line of the memory chip are connected to each other, a second signal line and a first signal line of the memory chip are connected to each other. Besides, the second power line and the second ground line are respectively connected to the wide power bus and the wide ground bus. An extremity of respectively, wide power bus, wide ground bus, and second signal line is exposed at the surface of the thick metal structure.
According to an embodiment of the invention, a first surface of the memory chip further comprises a first passivation layer, wherein the first passivation layer wraps the plurality of first power bonding pads, the plurality of first ground bonding pads and the plurality of first signal bonding pads. Moreover, the first surface of the thick metal structure described above also comprises a second passivation layer, wherein the second passivation layer covers at least a second power bonding pad, at least a first ground bonding pad, and a plurality of second signal bonding pads. Besides, the thick metal structure of the invention further comprises an embedded capacitor therein. The said capacitor comprises a power source metallic plate, a ground metallic plate, and a dielectric layer between the power source plate and the ground plate. The material of the said dielectric layer may be comprised of Ta
2
O
5
, and benzocyclobutene. In the thick metal structure, the material of the patt

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