Whole-chip ESD protection for CMOS ICs using bi-directional SCRs

Details Whole-chip ESD protection for CMOS ICs using bi-directional SCRs Whole-chip ESD protection for CMOS ICs using bi-directional SCRs

1998-08-26

2000-01-04

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 56, 361 915, H02H 322

Patent

active

060116811

ABSTRACT:
CMOS VLSI chips with pin counts greater than 100 often have multiple power pins to supply sufficient current for circuit operations. In mixed voltage ICs there are separated power pins with different power supplies for specified power operations, and in these ICs the power supplies for the digital and analog circuits are often separated due to noise considerations. In such ICs with separated power pins, the interface circuits between the circuits with different power pins are vulnerable to ESD (electrostatic discharge) stress. Even though there are suitable ESD protection circuits around the input and output pins of the IC, unexpected ESD damage still happens to the interface circuits between the circuits with different power pins, so that a whole-chip ESD protection arrangement using bi-directional SCRs is provided to protect the CMOS ICs against ESD damage. The bi-directional SCRs are placed between the separated power lines of the CMOS IC to provide ESD current discharging paths between the separated power lines. Thus, the vulnerable internal circuits and interface circuits between the different power pins are rendered remote from the ESD damage. The present ESD protection arrangement can be applied to chips having multiple or mixed-voltage power pins.

REFERENCES:
patent: 5392185 (1995-02-01), Haas, Jr. et al.
patent: 5530612 (1996-06-01), Maloney
patent: 5719733 (1998-02-01), Wei et al.
patent: 5754381 (1998-05-01), Ker

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