Whole chip ESD protection

Details Whole chip ESD protection Whole chip ESD protection

2005-04-12

2005-04-12

Nelms, David (Department: 2818)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S320000

Reexamination Certificate

active

06879203

ABSTRACT:
This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

REFERENCES:
patent: 5818087 (1998-10-01), Yee
patent: 6218704 (2001-04-01), Brown et al.
patent: 6262873 (2001-07-01), Pequignot et al.
patent: 6344412 (2002-02-01), Ichikawa et al.

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