Wet clean of organic silicate glass films

Details Wet clean of organic silicate glass films Wet clean of organic silicate glass films

2000-08-31

2003-04-22

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S745000, C438S746000, C134S001100, C134S001200, C134S001300

Reexamination Certificate

active

06551943

ABSTRACT:

FIELD OF THE INVENTION
The invention is generally related to the field of forming interconnect layers in semiconductor devices and more specifically to interconnect layers having organic silicate glass dielectric films.
BACKGROUND OF THE INVENTION
As the density of semiconductor devices increases, the demands on interconnect layers for connecting the semiconductor devices to each other also increases. Therefore, there is a desire to switch from the traditional aluminum metal interconnects to copper interconnects. Unfortunately, suitable copper etches for a semiconductor fabrication environment are not readily available. To overcome the copper etch problem, damascene processes have been developed.
In a damascene process, the IMD
16
is formed first. The IMD
16
is then patterned and etched to form a trench for the interconnect line. If connection vias have not already been formed, a dual damascene process may be used. In a dual damascene process, after the trench is formed in the IMD, a via is etched in the ILD
12
for connection to lower interconnect levels. The barrier layer
14
and a copper seed layer are then deposited over the structure. The barrier layer
14
is typically tantalum nitride or some other binary transition metal nitride. The copper layer is the formed using the seed layer over the entire structure. The copper is then chemically-mechanically polished (CMP'd) to remove the copper from over the IMD
16
, leaving copper interconnect lines
18
and vias
20
as shown in
FIG. 1. A
metal etch is thereby avoided.
Further improvements in interconnect performance are desired. Accordingly, efforts are being made to include low-k dielectric materials in a copper interconnect structure. One such low-k dielectric is called organic silicate glass (OSG). OSG is defined as a carbon based polymer doped with silicon. As these materials are new to semiconductor processing, sub-processes for incorporating these materials in a process flow are needed. For example, after the trench and via etches described above, a clean up process is required to remove etch residues. The polymer nature of OSG can easily be degraded by chemical treatment.
SUMMARY OF THE INVENTION
The invention is a post-etch clean up process for OSG. After an etch, a wet chemistry comprising HF and H
2
O
2
is used to remove residues without etching or damaging the OSG film.
An advantage of the invention is providing a clean process that is compatible with OSG and the copper surface.
This and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.


REFERENCES:
patent: 5814186 (1998-09-01), Nguyen
patent: 5886410 (1999-03-01), Chiang et al.
patent: 6093635 (2000-07-01), Tran et al.
patent: 6117785 (2000-09-01), Lee et al.
patent: 6168726 (2001-01-01), Li et al.
patent: 6242165 (2001-06-01), Vaartstra

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