Well isolation trenches (WIT) for CMOS devices

Details Well isolation trenches (WIT) for CMOS devices Well isolation trenches (WIT) for CMOS devices

2007-06-08

2010-06-15

Jackson, Jr., Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S371000, C257SE21545, C257SE29021

Reexamination Certificate

active

07737504

ABSTRACT:
A well isolation trenches for a CMOS device and the method for forming the same. The CMOS device includes (a) a semiconductor substrate, (b) a P well and an N well in the semiconductor substrate, (c) a well isolation region sandwiched between and in direct physical contact with the P well and the N well. The P well comprises a first shallow trench isolation (STI) region, and the N well comprises a second STI region. A bottom surface of the well isolation region is at a lower level than bottom surfaces of the first and second STI regions. When going from top to bottom of the well isolation region, an area of a horizontal cross section of the well isolation region is an essentially continuous function.

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